From patchwork Mon Jul 10 15:46:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Abreu X-Patchwork-Id: 786248 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3x5qQT4JDdz9s78 for ; Tue, 11 Jul 2017 01:49:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754132AbdGJPra (ORCPT ); Mon, 10 Jul 2017 11:47:30 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:60975 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753593AbdGJPr3 (ORCPT ); Mon, 10 Jul 2017 11:47:29 -0400 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id EE09724E041F; Mon, 10 Jul 2017 08:47:28 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id D1FD426B; Mon, 10 Jul 2017 08:47:28 -0700 (PDT) Received: from joabreu-VirtualBox.internal.synopsys.com (joabreu-e7440.internal.synopsys.com [10.107.19.85]) by mailhost.synopsys.com (Postfix) with ESMTP id 942FB233; Mon, 10 Jul 2017 08:47:26 -0700 (PDT) From: Jose Abreu To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jose Abreu , Carlos Palminha , Rob Herring , Mark Rutland , Mauro Carvalho Chehab , Hans Verkuil , Sylwester Nawrocki , devicetree@vger.kernel.org Subject: [PATCH v8 2/5] dt-bindings: media: Document Synopsys Designware HDMI RX Date: Mon, 10 Jul 2017 16:46:52 +0100 Message-Id: <36ad6ab0cf3051efeb02508141e08efd56761018.1499701282.git.joabreu@synopsys.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for the Synopsys Designware HDMI RX. Signed-off-by: Jose Abreu Cc: Carlos Palminha Cc: Rob Herring Cc: Mark Rutland Cc: Mauro Carvalho Chehab Cc: Hans Verkuil Cc: Sylwester Nawrocki Cc: devicetree@vger.kernel.org Changes from v7: - Remove SoC specific bindings (Rob) Changes from v6: - Document which properties are required/optional (Sylwester) - Drop compatible string for SoC (Sylwester) - Reword edid-phandle property (Sylwester) - Typo fixes (Sylwester) Changes from v4: - Use "cfg" instead of "cfg-clk" (Rob) - Change node names (Rob) Changes from v3: - Document the new DT bindings suggested by Sylwester Changes from v2: - Document edid-phandle property Acked-by: Rob Herring --- .../devicetree/bindings/media/snps,dw-hdmi-rx.txt | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt diff --git a/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt new file mode 100644 index 0000000..1dc09c6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/snps,dw-hdmi-rx.txt @@ -0,0 +1,58 @@ +Synopsys DesignWare HDMI RX Decoder +=================================== + +This document defines device tree properties for the Synopsys DesignWare HDMI +RX Decoder (DWC HDMI RX). + +The properties bellow belong to the Synopsys DesignWare HDMI RX Decoder node. + +Required properties: + +- compatible: Shall be "snps,dw-hdmi-rx". +- reg: Memory mapped base address and length of the DWC HDMI RX registers. +- interrupts: Reference to the DWC HDMI RX interrupt and the HDMI 5V sense +interrupt. +- clocks: Reference to the config clock. +- clock-names: Shall be "cfg". +- #address-cells: Shall be 1. +- #size-cells: Shall be 0. + +Optional properties: + +- edid-phandle: Reference to the EDID handler block; if this property is not +specified it is assumed that EDID is handled by device described by parent +node of the HDMI RX node. You should not specify this property if your HDMI RX +controller does not have CEC. + +You also have to create a subnode for the PHY device. PHY node properties are +as follows. + +Required properties: + +- compatible: Shall be "snps,dw-hdmi-phy-e405". +- reg: Shall be the JTAG address of the PHY. +- clocks: Reference to the config clock. +- clock-names: Shall be "cfg". + +Example: + +hdmi_rx: hdmi-rx@0 { + compatible = "snps,dw-hdmi-rx"; + reg = <0x0 0x10000>; + interrupts = <1 2>; + edid-phandle = <&dw_hdmi_edid>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + + #address-cells = <1>; + #size-cells = <0>; + + hdmi-phy@fc { + compatible = "snps,dw-hdmi-phy-e405"; + reg = <0xfc>; + + clocks = <&dw_hdmi_refclk>; + clock-names = "cfg"; + }; +};