| Message ID | 20240925001628.669604-1-marex@denx.de |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/2] arm64: dts: imx8mp: Document DH i.MX8MP DHCOM SoM on DRC02 carrier board | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 7 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 9/25/24 2:15 AM, Marek Vasut wrote: > Document support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. > This system is populated with two ethernet ports, two CANs, RS485 and RS232, > USB, capacitive buttons and an OLED display. Subject prefix should be dt-bindings: arm: fsl: , will be fixed in V2.
On Wed, 25 Sep 2024 02:15:16 +0200, Marek Vasut wrote: > Document support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. > This system is populated with two ethernet ports, two CANs, RS485 and RS232, > USB, capacitive buttons and an OLED display. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Gregor Herburger <gregor.herburger@ew.tq-group.com> > Cc: Hiago De Franco <hiago.franco@toradex.com> > Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com> > Cc: Joao Paulo Goncalves <joao.goncalves@toradex.com> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Mathieu Othacehe <m.othacehe@gmail.com> > Cc: Max Merchel <Max.Merchel@ew.tq-group.com> > Cc: Michael Walle <mwalle@kernel.org> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 1 + > 1 file changed, 1 insertion(+) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y freescale/imx8mp-dhcom-drc02.dtb' for 20240925001628.669604-1-marex@denx.de: arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dtb: pcie-ep@33800000: reg: [[864026624, 4194304], [402653184, 134217728]] is too short from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml# arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dtb: pcie-ep@33800000: reg-names: ['dbi', 'addr_space'] is too short from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
On Wed, Sep 25, 2024 at 02:15:17AM +0200, Marek Vasut wrote: > Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. > This system is populated with two ethernet ports, two CANs, RS485 and RS232, > USB, capacitive buttons and an OLED display. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > Cc: Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Fabio Estevam <festevam@gmail.com> > Cc: Gregor Herburger <gregor.herburger@ew.tq-group.com> > Cc: Hiago De Franco <hiago.franco@toradex.com> > Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com> > Cc: Joao Paulo Goncalves <joao.goncalves@toradex.com> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Mathieu Othacehe <m.othacehe@gmail.com> > Cc: Max Merchel <Max.Merchel@ew.tq-group.com> > Cc: Michael Walle <mwalle@kernel.org> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Sascha Hauer <s.hauer@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: imx@lists.linux.dev > Cc: linux-arm-kernel@lists.infradead.org > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mp-dhcom-drc02.dts | 255 ++++++++++++++++++ > 2 files changed, 256 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 9d3df8b218a2e..f6b8041c1e8f7 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -167,6 +167,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts > new file mode 100644 > index 0000000000000..c6bf7fd919814 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts > @@ -0,0 +1,255 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2024 Marek Vasut <marex@denx.de> > + * > + * DHCOM iMX8MP variant: > + * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2 > + * DHCOM PCB number: 660-100 or newer > + * DRC02 PCB number: 568-100 or newer > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/leds/common.h> > +#include <dt-bindings/phy/phy-imx8-pcie.h> > +#include "imx8mp-dhcom-som.dtsi" > + > +/ { > + model = "DH electronics i.MX8M Plus DHCOM on DRC02"; > + compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som", > + "fsl,imx8mp"; > + > + chosen { > + stdout-path = &uart1; > + }; > +}; > + > +&eqos { /* First ethernet */ > + pinctrl-0 = <&pinctrl_eqos_rmii>; > + phy-handle = <ðphy0f>; > + phy-mode = "rmii"; > + > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, > + <&clk IMX8MP_SYS_PLL2_100M>, > + <&clk IMX8MP_SYS_PLL2_50M>; > + assigned-clock-rates = <0>, <100000000>, <50000000>; > +}; > + > +ðphy0g { /* Micrel KSZ9131RNXI */ > + status = "disabled"; > +}; > + > +ðphy0f { /* SMSC LAN8740Ai */ > + status = "okay"; > +}; > + > +&fec { /* Second ethernet */ > + pinctrl-0 = <&pinctrl_fec_rmii>; > + phy-handle = <ðphy1f>; > + phy-mode = "rmii"; > + status = "okay"; > + > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, > + <&clk IMX8MP_SYS_PLL2_100M>, > + <&clk IMX8MP_SYS_PLL2_50M>, > + <&clk IMX8MP_SYS_PLL2_50M>; > + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; > +}; > + > +ðphy1f { /* SMSC LAN8740Ai */ > + status = "okay"; > +}; > + > +&flexcan1 { > + status = "okay"; > +}; > + > +&flexcan2 { > + status = "okay"; > +}; > + > +&gpio1 { > + gpio-line-names = > + "DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0", > + "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", > + "", "", "", "", "", "", "", "", > + "", "", "", "", "", "", "", ""; > + > + /* > + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate > + * GPIO line, however the i.MX8 UART driver assumes RX happens > + * during TX anyway and that it only controls drive enable DE > + * line. Hence, the RX is always enabled here. > + */ > + rs485-rx-en-hog { > + gpio-hog; > + gpios = <13 0>; /* GPIO Q */ > + line-name = "rs485-rx-en"; > + output-low; > + }; > +}; > + > +&gpio2 { > + gpio-line-names = > + "", "", "", "", "", "", "", "", > + "DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "", > + "", "", "", "", "DRC02-In2", "", "", "", > + "", "", "", "", "", "", "", ""; > +}; > + > +&gpio3 { > + gpio-line-names = > + "", "", "", "", "", "", "", "", > + "", "", "", "", "", "", "SOM-HW0", "", > + "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", > + "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; > +}; > + > +&gpio4 { > + gpio-line-names = > + "", "", "", "", "", "", "", "", > + "", "", "", "", "", "", "", "", > + "", "", "", "SOM-HW1", "", "", "", "", > + "", "", "", "DRC02-Out2", "", "", "", ""; > +}; > + > +&gpio5 { > + gpio-line-names = > + "", "", "DHCOM-C", "", "", "", "", "", > + "", "", "", "", "", "", "", "", > + "", "", "", "", "", "", "DHCOM-E", "DRC02-Out1", > + "", "", "", "", "", "", "", ""; > +}; > + > +/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */ > +&hdmi_blk_ctrl { > + status = "disabled"; > +}; > + > +&hdmi_pvi { > + status = "disabled"; > +}; > + > +&hdmi_tx { > + status = "disabled"; > +}; > + > +&hdmi_tx_phy { > + status = "disabled"; > +}; > + > +&i2c3 { > + /* Resistive touch controller not populated on this one SoM variant. */ > + touchscreen@49 { > + status = "disabled"; > + }; > +}; > + > +&irqsteer_hdmi { > + status = "disabled"; > +}; > + > +&lcdif3 { > + status = "disabled"; > +}; > + > +&pcie_phy { > + status = "disabled"; > +}; > + > +&pcie { > + status = "disabled"; > +}; > + > +/* Console UART */ > +&pinctrl_uart1 { > + fsl,pins = < > + /* No pull-ups on DRC02, enable in-SoC pull-ups */ > + MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149 > + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149 > + >; > +}; > + > +&pinctrl_uart3 { > + fsl,pins = < > + /* No pull-ups on DRC02, enable in-SoC pull-ups */ > + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149 > + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149 > + >; > +}; > + > +&uart1 { > + /* > + * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to > + * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs > + * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS. > + */ > + /delete-property/ uart-has-rtscts; > + cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */ > + pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; > + pinctrl-names = "default"; > + rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ > +}; > + > +&uart3 { > + /* > + * On DRC02 this UART is used as RS485 interface and RS485_TX_En is > + * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property > + * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via > + * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 > + * node above. > + */ > + /delete-property/ uart-has-rtscts; > + linux,rs485-enabled-at-boot-time; > + pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>; > + pinctrl-names = "default"; > + rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */ > +}; > + > +/* No WiFi/BT chipset on this SoM variant. */ > +&uart2 { > + bluetooth { > + status = "disabled"; > + }; > +}; > + > +/* USB_OTG port is not routed out on DRC02. */ > +&usb3_0 { > + status = "disabled"; > +}; > + > +&usb_dwc3_0 { > + status = "disabled"; > +}; > + > +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ > +&usb3_1 { > + fsl,disable-port-power-control; > + fsl,permanently-attached; > +}; Suggest run https://github.com/lznuaa/dt-format to sort node &usb_dwc3_0 &usb_dwc3_1 &usb3_0 &usb3_1 Any issue about tools, let me know. Frank > + > +&usb_dwc3_1 { > + dr_mode = "host"; > + maximum-speed = "high-speed"; > +}; > + > +/* No WiFi/BT chipset on this SoM variant. */ > +&usdhc1 { > + status = "disabled"; > +}; > + > +&iomuxc { > + /* > + * GPIO I is connected to UART1_RTS > + * GPIO M is connected to UART1_CTS > + * GPIO P is connected to RS485_TX_En > + * GPIO Q is connected to RS485_RX_En > + */ > + pinctrl-0 = <&pinctrl_hog_base > + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c > + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f > + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j > + &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n > + &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s > + &pinctrl_dhcom_int>; > +}; > -- > 2.45.2 >
On 9/25/24 6:30 PM, Frank Li wrote: [...] >> +/* USB_OTG port is not routed out on DRC02. */ >> +&usb3_0 { >> + status = "disabled"; >> +}; >> + >> +&usb_dwc3_0 { >> + status = "disabled"; >> +}; >> + >> +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ >> +&usb3_1 { >> + fsl,disable-port-power-control; >> + fsl,permanently-attached; >> +}; > > Suggest run https://github.com/lznuaa/dt-format to sort node > > &usb_dwc3_0 > &usb_dwc3_1 > &usb3_0 > &usb3_1 I'm afraid the tool (I did not try it, I used plain GNU sort) is not sorting this correctly, look at ASCII table, 0x33 is '3' and 0x5f is '_': $ printf 3_ | hexdump -vC 00000000 33 5f So if the sorting was correct, it would be: usb3_0 usb3_1 usb_dwc3_0 usb_dwc3_1 But I would prefer to keep the controllers close to each other, i.e. the current order which seems more logical in this case: usb3_0 usb_dwc3_0 usb3_1 usb_dwc3_1 [...]
On Wed, Sep 25, 2024 at 11:09:13PM +0200, Marek Vasut wrote: > On 9/25/24 6:30 PM, Frank Li wrote: > > [...] > > > > +/* USB_OTG port is not routed out on DRC02. */ > > > +&usb3_0 { > > > + status = "disabled"; > > > +}; > > > + > > > +&usb_dwc3_0 { > > > + status = "disabled"; > > > +}; > > > + > > > +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ > > > +&usb3_1 { > > > + fsl,disable-port-power-control; > > > + fsl,permanently-attached; > > > +}; > > > > Suggest run https://github.com/lznuaa/dt-format to sort node > > > > &usb_dwc3_0 > > &usb_dwc3_1 > > &usb3_0 > > &usb3_1 > > I'm afraid the tool (I did not try it, I used plain GNU sort) is not sorting > this correctly, look at ASCII table, 0x33 is '3' and 0x5f is '_': > > $ printf 3_ | hexdump -vC > 00000000 33 5f Sorry, I have not run it for this dts. I make misstake - and _ at ascii table. > > So if the sorting was correct, it would be: > > usb3_0 > usb3_1 > usb_dwc3_0 > usb_dwc3_1 > > But I would prefer to keep the controllers close to each other, i.e. the > current order which seems more logical in this case: > > usb3_0 > usb_dwc3_0 > usb3_1 > usb_dwc3_1 next time, we should use better label name in chip.dtsi file. I try to reduce trivial node name order issue in patch review. And make contributor to be easy to follow. Frank > > [...]
On 9/25/24 11:27 PM, Frank Li wrote: Hi, >>>> +/* USB_OTG port is not routed out on DRC02. */ >>>> +&usb3_0 { >>>> + status = "disabled"; >>>> +}; >>>> + >>>> +&usb_dwc3_0 { >>>> + status = "disabled"; >>>> +}; >>>> + >>>> +/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */ >>>> +&usb3_1 { >>>> + fsl,disable-port-power-control; >>>> + fsl,permanently-attached; >>>> +}; >>> >>> Suggest run https://github.com/lznuaa/dt-format to sort node >>> >>> &usb_dwc3_0 >>> &usb_dwc3_1 >>> &usb3_0 >>> &usb3_1 >> >> I'm afraid the tool (I did not try it, I used plain GNU sort) is not sorting >> this correctly, look at ASCII table, 0x33 is '3' and 0x5f is '_': >> >> $ printf 3_ | hexdump -vC >> 00000000 33 5f > > Sorry, I have not run it for this dts. I make misstake - and _ at ascii > table. No worries >> So if the sorting was correct, it would be: >> >> usb3_0 >> usb3_1 >> usb_dwc3_0 >> usb_dwc3_1 >> >> But I would prefer to keep the controllers close to each other, i.e. the >> current order which seems more logical in this case: >> >> usb3_0 >> usb_dwc3_0 >> usb3_1 >> usb_dwc3_1 > > next time, we should use better label name in chip.dtsi file. I try to > reduce trivial node name order issue in patch review. And make contributor > to be easy to follow. I suspect the dwc3_0 and co. is somewhat inherited from other DTs which used the controller before.
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b39a7e031177e..09027a4ef515c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1100,6 +1100,7 @@ properties: - description: i.MX8MP DHCOM based Boards items: - enum: + - dh,imx8mp-dhcom-drc02 # i.MX8MP DHCOM SoM on DRC02 board - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board - dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board - const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
Document support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. This system is populated with two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Alexander Stein <alexander.stein@ew.tq-group.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Gregor Herburger <gregor.herburger@ew.tq-group.com> Cc: Hiago De Franco <hiago.franco@toradex.com> Cc: Hugo Villeneuve <hvilleneuve@dimonoff.com> Cc: Joao Paulo Goncalves <joao.goncalves@toradex.com> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Mathieu Othacehe <m.othacehe@gmail.com> Cc: Max Merchel <Max.Merchel@ew.tq-group.com> Cc: Michael Walle <mwalle@kernel.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Rob Herring <robh@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: devicetree@vger.kernel.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+)