| Message ID | 20240916064706.318793-2-18771902331@163.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add initial support for Canaan Kendryte K230 pinctrl | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 2 warnings, 339 lines checked |
| robh/patch-applied | success |
On 16/09/2024 08:47, Ze Huang wrote: > Add pinctrl device, containing default config for uart, pwm, iis, iic and > mmc. > > Signed-off-by: Ze Huang <18771902331@163.com> > --- > arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ > arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ > arch/riscv/boot/dts/canaan/k230.dtsi | 2 + > 3 files changed, 336 insertions(+) > create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h > > diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > new file mode 100644 > index 000000000000..0737f50d2868 > --- /dev/null > +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > @@ -0,0 +1,316 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (C) 2024 Ze Huang <18771902331@163.com> > + */ > +#include "k230-pinctrl.h" > + > +/ { > + soc { > + pinctrl: pinctrl@91105000 { That's odd style - defining SoC nodes outside of SoC DTSI. Are you sure that's preferred coding style in RISC-V or Canaan? > + compatible = "canaan,k230-pinctrl"; > + reg = <0x0 0x91105000 0x0 0x100>; > + Best regards, Krzysztof
On 9/16/24 11:52 PM, Krzysztof Kozlowski wrote: > On 16/09/2024 08:47, Ze Huang wrote: >> Add pinctrl device, containing default config for uart, pwm, iis, iic and >> mmc. >> >> Signed-off-by: Ze Huang <18771902331@163.com> >> --- >> arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ >> arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ >> arch/riscv/boot/dts/canaan/k230.dtsi | 2 + >> 3 files changed, 336 insertions(+) >> create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >> create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h >> >> diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >> new file mode 100644 >> index 000000000000..0737f50d2868 >> --- /dev/null >> +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >> @@ -0,0 +1,316 @@ >> +// SPDX-License-Identifier: GPL-2.0 OR MIT >> +/* >> + * Copyright (C) 2024 Ze Huang <18771902331@163.com> >> + */ >> +#include "k230-pinctrl.h" >> + >> +/ { >> + soc { >> + pinctrl: pinctrl@91105000 { > That's odd style - defining SoC nodes outside of SoC DTSI. Are you sure > that's preferred coding style in RISC-V or Canaan? Pinctrl-related nodes were separated the for ease of maintenance, but the convention in Canaan is to place them in the board-level DTS file. Would it be better to stay consistent with their approach? >> + compatible = "canaan,k230-pinctrl"; >> + reg = <0x0 0x91105000 0x0 0x100>; >> + > Best regards, > Krzysztof
On Wed, Sep 18, 2024 at 04:39:29PM +0800, Ze Huang wrote: > On 9/16/24 11:52 PM, Krzysztof Kozlowski wrote: > > On 16/09/2024 08:47, Ze Huang wrote: > > > Add pinctrl device, containing default config for uart, pwm, iis, iic and > > > mmc. > > > > > > Signed-off-by: Ze Huang <18771902331@163.com> > > > --- > > > arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ > > > arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ > > > arch/riscv/boot/dts/canaan/k230.dtsi | 2 + > > > 3 files changed, 336 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > > > create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h > > > > > > diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > > > new file mode 100644 > > > index 000000000000..0737f50d2868 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi > > > @@ -0,0 +1,316 @@ > > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > > +/* > > > + * Copyright (C) 2024 Ze Huang <18771902331@163.com> > > > + */ > > > +#include "k230-pinctrl.h" > > > + > > > +/ { > > > + soc { > > > + pinctrl: pinctrl@91105000 { > > That's odd style - defining SoC nodes outside of SoC DTSI. Are you sure > > that's preferred coding style in RISC-V or Canaan? > > Pinctrl-related nodes were separated the for ease of maintenance, but the > convention in Canaan is to place them in the board-level DTS file. Would it > be better to stay consistent with their approach? Yeah, please put them in the board-level file. Thanks, Conor.
On 9/23/24 5:50 PM, Conor Dooley wrote: > On Wed, Sep 18, 2024 at 04:39:29PM +0800, Ze Huang wrote: >> On 9/16/24 11:52 PM, Krzysztof Kozlowski wrote: >>> On 16/09/2024 08:47, Ze Huang wrote: >>>> Add pinctrl device, containing default config for uart, pwm, iis, iic and >>>> mmc. >>>> >>>> Signed-off-by: Ze Huang <18771902331@163.com> >>>> --- >>>> arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ >>>> arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ >>>> arch/riscv/boot/dts/canaan/k230.dtsi | 2 + >>>> 3 files changed, 336 insertions(+) >>>> create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >>>> create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h >>>> >>>> diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >>>> new file mode 100644 >>>> index 000000000000..0737f50d2868 >>>> --- /dev/null >>>> +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi >>>> @@ -0,0 +1,316 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 OR MIT >>>> +/* >>>> + * Copyright (C) 2024 Ze Huang <18771902331@163.com> >>>> + */ >>>> +#include "k230-pinctrl.h" >>>> + >>>> +/ { >>>> + soc { >>>> + pinctrl: pinctrl@91105000 { >>> That's odd style - defining SoC nodes outside of SoC DTSI. Are you sure >>> that's preferred coding style in RISC-V or Canaan? >> Pinctrl-related nodes were separated the for ease of maintenance, but the >> convention in Canaan is to place them in the board-level DTS file. Would it >> be better to stay consistent with their approach? > Yeah, please put them in the board-level file. OK > > Thanks, > Conor.
diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi new file mode 100644 index 000000000000..0737f50d2868 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ +#include "k230-pinctrl.h" + +/ { + soc { + pinctrl: pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x0 0x91105000 0x0 0x100>; + + jtag_pins: jtag-pins { + jtag-tck-cfg { + pinmux = <K230_PINMUX(2, 1)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-pull-down; + input-schmitt-enable; + }; + + jtag-tdi-cfg { + pinmux = <K230_PINMUX(3, 1)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-disable; + }; + + jtag-tdo-cfg { + pinmux = <K230_PINMUX(4, 1)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + }; + + jtag-tms-cfg { + pinmux = <K230_PINMUX(5, 1)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux = <K230_PINMUX(5, 3)>, /* uart2 txd */ + <K230_PINMUX(6, 3)>; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-disable; + }; + }; + + pwm2_pins: pwm2-pins { + pwm2-pin-cfg { + pinmux = <K230_PINMUX(7, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm3_pins: pwm3-pins { + pwm3-pin-cfg { + pinmux = <K230_PINMUX(8, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm4_pins: pwm4-pins { + pwm4-pin-cfg { + pinmux = <K230_PINMUX(9, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iis_pins: iis-pins { + iis-clk-cfg { + pinmux = <K230_PINMUX(32, 2)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + }; + + iis-ws-cfg { + pinmux = <K230_PINMUX(33, 2)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + }; + + iis-din0-cfg { + pinmux = <K230_PINMUX(34, 2)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-disable; + }; + + iis-dout0-cfg { + pinmux = <K230_PINMUX(35, 2)>; + slew-rate = <0>; + drive-strength = <4>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + }; + }; + + uart4_pins: uart4-pins { + uart4-txd-cfg { + pinmux = <K230_PINMUX(36, 4)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart4-rxd-cfg { + pinmux = <K230_PINMUX(37, 4)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0-txd-cfg { + pinmux = <K230_PINMUX(38, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart0-rxd-cfg { + pinmux = <K230_PINMUX(39, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iic1_pins: iic1-pins { + iic1-pins-cfg { + pinmux = <K230_PINMUX(40, 2)>, /* iic1 scl */ + <K230_PINMUX(41, 2)>; /* iic1 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic3_pins: iic3-pins { + iic3-pins-cfg { + pinmux = <K230_PINMUX(44, 2)>, /* iic3 scl */ + <K230_PINMUX(45, 2)>; /* iic3 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic4_pins: iic4-pins { + iic4-pins-cfg { + pinmux = <K230_PINMUX(46, 3)>, /* iic4 scl */ + <K230_PINMUX(47, 3)>; /* iic4 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic0_pins: iic0-pins { + iic0-pins-cfg { + pinmux = <K230_PINMUX(48, 3)>, /* iic0 scl */ + <K230_PINMUX(49, 3)>; /* iic0 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_1V8>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-pins { + uart3-txd-cfg { + pinmux = <K230_PINMUX(50, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart3-rxd-cfg { + pinmux = <K230_PINMUX(51, 1)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + key_pins: key-pins { + key-pins-cfg { + pinmux = <K230_PINMUX(52, 0)>, /* key0 */ + <K230_PINMUX(53, 0)>; /* key1 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + mmc1_pins: mmc1-pins { + mmc1-cmd-cfg { + pinmux = <K230_PINMUX(54, 2)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + + mmc1-clk-cfg { + pinmux = <K230_PINMUX(55, 2)>; + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + mmc1-data-cfg { + pinmux = <K230_PINMUX(56, 2)>, /* mmc1 data0 */ + <K230_PINMUX(57, 2)>, /* mmc1 data1 */ + <K230_PINMUX(58, 2)>, /* mmc1 data2 */ + <K230_PINMUX(59, 2)>; /* mmc1 data3 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = <K230_MSC_3V3>; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dts/canaan/k230-pinctrl.h new file mode 100644 index 000000000000..f240a980f37a --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ + +#ifndef _K230_PINCTRL_H +#define _K230_PINCTRL_H + +#define K230_MSC_3V3 0 +#define K230_MSC_1V8 1 + +#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 + +#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode)) + +#endif /* _K230_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 95c1a3d8fb11..a9354e538642 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -140,3 +140,5 @@ uart4: serial@91404000 { }; }; }; + +#include "k230-pinctrl.dtsi"
Add pinctrl device, containing default config for uart, pwm, iis, iic and mmc. Signed-off-by: Ze Huang <18771902331@163.com> --- arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi | 316 +++++++++++++++++++ arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ arch/riscv/boot/dts/canaan/k230.dtsi | 2 + 3 files changed, 336 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h