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Fri, 26 Jul 2024 01:26:50 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 26 Jul 2024 01:26:46 -0500 From: Abin Joseph To: , , , , , , , CC: , , , , , Subject: [PATCH 1/2] dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string Date: Fri, 26 Jul 2024 11:56:38 +0530 Message-ID: <20240726062639.2609974-2-abin.joseph@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726062639.2609974-1-abin.joseph@amd.com> References: <20240726062639.2609974-1-abin.joseph@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|PH7PR12MB7235:EE_ X-MS-Office365-Filtering-Correlation-Id: 1595868e-ef9d-4097-ce8d-08dcad3befee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2024 06:26:51.6567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1595868e-ef9d-4097-ce8d-08dcad3befee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7235 Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2 platform. AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general purpose DMAs which is designed to support memory to memory and memory to IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register offset. Add example binding documentation for the newly added compatible string. Signed-off-by: Abin Joseph --- .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index 769ce23aaac2..17f16ae7e42b 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -24,7 +24,9 @@ properties: const: 1 compatible: - const: xlnx,zynqmp-dma-1.0 + enum: + - xlnx,zynqmp-dma-1.0 + - amd,versal2-dma-1.0 reg: description: memory map for gdma/adma module access @@ -74,6 +76,7 @@ additionalProperties: false examples: - | #include + #include fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -86,3 +89,15 @@ examples: xlnx,bus-width = <128>; dma-coherent; }; + + fpd_dma_chan2: dma-controller@ebd00000 { + compatible = "amd,versal2-dma-1.0"; + reg = <0xebd00000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + #dma-cells = <1>; + clock-names = "clk_main", "clk_apb"; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + xlnx,bus-width = <128>; + dma-coherent; + };