| Message ID | 20240726062639.2609974-2-abin.joseph@amd.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for ADMA | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 26/07/2024 08:26, Abin Joseph wrote: > Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2 > platform. > > AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general > purpose DMAs which is designed to support memory to memory and memory to > IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register > offset. Add example binding documentation for the newly added compatible > string. > > Signed-off-by: Abin Joseph <abin.joseph@amd.com> > --- > .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml > index 769ce23aaac2..17f16ae7e42b 100644 > --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml > +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml > @@ -24,7 +24,9 @@ properties: > const: 1 > > compatible: > - const: xlnx,zynqmp-dma-1.0 > + enum: > + - xlnx,zynqmp-dma-1.0 > + - amd,versal2-dma-1.0 Keep the list ordered. > > reg: > description: memory map for gdma/adma module access > @@ -74,6 +76,7 @@ additionalProperties: false > examples: > - | > #include <dt-bindings/clock/xlnx-zynqmp-clk.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > fpd_dma_chan1: dma-controller@fd500000 { > compatible = "xlnx,zynqmp-dma-1.0"; > @@ -86,3 +89,15 @@ examples: > xlnx,bus-width = <128>; > dma-coherent; > }; > + > + fpd_dma_chan2: dma-controller@ebd00000 { That's the same example. Xilinx already received such comments, so finally please learn them. Drop the example. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index 769ce23aaac2..17f16ae7e42b 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -24,7 +24,9 @@ properties: const: 1 compatible: - const: xlnx,zynqmp-dma-1.0 + enum: + - xlnx,zynqmp-dma-1.0 + - amd,versal2-dma-1.0 reg: description: memory map for gdma/adma module access @@ -74,6 +76,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/xlnx-zynqmp-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -86,3 +89,15 @@ examples: xlnx,bus-width = <128>; dma-coherent; }; + + fpd_dma_chan2: dma-controller@ebd00000 { + compatible = "amd,versal2-dma-1.0"; + reg = <0xebd00000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clock-names = "clk_main", "clk_apb"; + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + xlnx,bus-width = <128>; + dma-coherent; + };
Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2 platform. AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general purpose DMAs which is designed to support memory to memory and memory to IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register offset. Add example binding documentation for the newly added compatible string. Signed-off-by: Abin Joseph <abin.joseph@amd.com> --- .../dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)