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25 Jul 2024 05:16:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 25 Jul 2024 05:16:34 -0700 Received: from ph-emdalo.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 25 Jul 2024 05:16:32 -0700 From: To: Conor Dooley , Daire McNamara , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" CC: Pierre-Henry Moussay , , , , Subject: [PATCH 07/17] dt-bindings: clock: mpfs-ccc: Add PIC64GX compatibility Date: Thu, 25 Jul 2024 13:15:59 +0100 Message-ID: <20240725121609.13101-8-pierre-henry.moussay@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> References: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Pierre-Henry Moussay PIC64GX SoC has clock compatibles with the MPFS IP Signed-off-by: Pierre-Henry Moussay --- .../devicetree/bindings/clock/microchip,mpfs-ccc.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml index f1770360798f..9a6b50527c42 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -17,7 +17,11 @@ description: | properties: compatible: - const: microchip,mpfs-ccc + oneOf: + - items: + - const: microchip,pic64gx-ccc + - const: microchip,mpfs-ccc + - const: microchip,mpfs-ccc reg: items: