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25 Jul 2024 05:16:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 25 Jul 2024 05:16:31 -0700 Received: from ph-emdalo.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 25 Jul 2024 05:16:29 -0700 From: To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou CC: Pierre-Henry Moussay , , , Subject: [PATCH 06/17] dt-bindings: riscv: sifive-l2: add a PIC64GX compatible Date: Thu, 25 Jul 2024 13:15:58 +0100 Message-ID: <20240725121609.13101-7-pierre-henry.moussay@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> References: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Pierre-Henry Moussay The PIC64GX use an IP similar to MPFS one, therefore add compatibility with MPFS as fallback Signed-off-by: Pierre-Henry Moussay --- Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..9d064feb2ab1 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -47,6 +47,11 @@ properties: - const: microchip,mpfs-ccache - const: sifive,fu540-c000-ccache - const: cache + - items: + - const: microchip,pic64gx-ccache + - const: microchip,mpfs-ccache + - const: sifive,fu540-c000-ccache + - const: cache cache-block-size: const: 64 @@ -93,6 +98,7 @@ allOf: - starfive,jh7100-ccache - starfive,jh7110-ccache - microchip,mpfs-ccache + - microchip,pic64gx-ccache then: properties: