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25 Jul 2024 05:16:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 25 Jul 2024 05:16:25 -0700 Received: from ph-emdalo.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 25 Jul 2024 05:16:23 -0700 From: To: Conor Dooley , Daire McNamara , Mark Brown , Rob Herring , Krzysztof Kozlowski CC: Pierre-Henry Moussay , , , , Subject: [PATCH 04/17] dt-bindings: spi: add PIC64GX SPI/QSPI compatibility to MPFS SPI/QSPI bindings Date: Thu, 25 Jul 2024 13:15:56 +0100 Message-ID: <20240725121609.13101-5-pierre-henry.moussay@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> References: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Pierre-Henry Moussay PIC64GX SPI/QSPI are compatible with MPFS SPI/QSPI driver, we just use fallback mechanism Signed-off-by: Pierre-Henry Moussay --- .../devicetree/bindings/spi/microchip,mpfs-spi.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml index 74a817cc7d94..4c9a7f1ade50 100644 --- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -20,9 +20,14 @@ properties: compatible: oneOf: - items: - - const: microchip,mpfs-qspi + - enum: + - microchip,mpfs-qspi + - microchip,pic64gx-qspi - const: microchip,coreqspi-rtl-v2 - const: microchip,coreqspi-rtl-v2 # FPGA QSPI + - items: + - const: microchip,pic64gx-spi + - const: microchip,mpfs-spi - const: microchip,mpfs-spi reg: