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25 Jul 2024 05:16:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 25 Jul 2024 05:16:43 -0700 Received: from ph-emdalo.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 25 Jul 2024 05:16:41 -0700 From: To: Conor Dooley , Daire McNamara , Andi Shyti , "Rob Herring" , Krzysztof Kozlowski CC: Pierre-Henry Moussay , , , , Subject: [PATCH 10/17] dt-bindings: i2c: microchip: corei2c: Add PIC64GX as compatible with driver Date: Thu, 25 Jul 2024 13:16:02 +0100 Message-ID: <20240725121609.13101-11-pierre-henry.moussay@microchip.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> References: <20240725121609.13101-1-pierre-henry.moussay@microchip.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Pierre-Henry Moussay PIC64GX i2c is compatible with the MPFS driver Signed-off-by: Pierre-Henry Moussay --- Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml index afa3db726229..4ba8a27eb8e5 100644 --- a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml +++ b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml @@ -18,6 +18,10 @@ properties: - items: - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core + - items: + - const: microchip,pic64gx-i2c + - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs + - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core reg: