| Message ID | 20240722062558.1578744-2-thippesw@amd.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add support for Xilinx XDMA Soft IP as Root Port | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote: > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > --- > .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- > 1 file changed, 39 insertions(+), 2 deletions(-) > --- > changes in v2 > - update dt node label with pcie. > --- > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > index 2f59b3a73dd2..28d9350a7fb4 100644 > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > @@ -14,10 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,xdma-host-3.00 > + enum: > + - xlnx,xdma-host-3.00 > + - xlnx,qdma-host-3.00 > > reg: > - maxItems: 1 > + items: > + - description: configuration region and XDMA bridge register. > + - description: QDMA bridge register. Please constrain the new entry to only the new compatible. > + minItems: 1 > + > + reg-names: > + items: > + - const: cfg > + - const: breg > + minItems: 1 > > ranges: > maxItems: 2 > @@ -111,4 +122,30 @@ examples: > interrupt-controller; > }; > }; > + > + pcie@80000000 { tbh, don't see the point of a new example for this. > + compatible = "xlnx,qdma-host-3.00"; > + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>; > + reg-names = "cfg", "breg"; > + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>, > + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "misc", "msi0", "msi1"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, > + <0 0 0 2 &pcie_intc_0 1>, > + <0 0 0 3 &pcie_intc_0 2>, > + <0 0 0 4 &pcie_intc_0 3>; > + pcie_intc_1: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > }; > -- > 2.25.1 >
Hi Conor Dooley, > -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: Monday, July 22, 2024 10:15 PM > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> > Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; linux- > pci@vger.kernel.org; Havalige, Thippeswamy > <thippeswamy.havalige@amd.com>; linux-arm-kernel@lists.infradead.org; > Simek, Michal <michal.simek@amd.com> > Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for > Xilinx QDMA PCIe Root Port Bridge > > On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote: > > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port > Bridge. > > > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > > --- > > .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- > > 1 file changed, 39 insertions(+), 2 deletions(-) > > --- > > changes in v2 > > - update dt node label with pcie. > > --- > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > index 2f59b3a73dd2..28d9350a7fb4 100644 > > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > @@ -14,10 +14,21 @@ allOf: > > > > properties: > > compatible: > > - const: xlnx,xdma-host-3.00 > > + enum: > > + - xlnx,xdma-host-3.00 > > + - xlnx,qdma-host-3.00 > > > > reg: > > - maxItems: 1 > > + items: > > + - description: configuration region and XDMA bridge register. > > + - description: QDMA bridge register. > > Please constrain the new entry to only the new compatible. - Thanks, I ll resend patch with required changes. > > > + minItems: 1 > > + > > + reg-names: > > + items: > > + - const: cfg > > + - const: breg > > + minItems: 1 > > > > ranges: > > maxItems: 2 > > @@ -111,4 +122,30 @@ examples: > > interrupt-controller; > > }; > > }; > > + > > + pcie@80000000 { > > tbh, don't see the point of a new example for this. - For this in both examples ranges properties are different. So, here I wanted to make sure that our example device tree bindings work straight forward when our reference designs are used. > > > + compatible = "xlnx,qdma-host-3.00"; > > + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 > 0x10000000>; > > + reg-names = "cfg", "breg"; > > + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 > 0x8000000>, > > + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 > 0x40000000>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + #interrupt-cells = <1>; > > + device_type = "pci"; > > + interrupt-parent = <&gic>; > > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 > IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "misc", "msi0", "msi1"; > > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > > + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, > > + <0 0 0 2 &pcie_intc_0 1>, > > + <0 0 0 3 &pcie_intc_0 2>, > > + <0 0 0 4 &pcie_intc_0 3>; > > + pcie_intc_1: interrupt-controller { > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + }; > > + }; > > }; > > -- > > 2.25.1 > > Regards, Thippeswamy H
On Wed, Jul 24, 2024 at 09:30:21AM +0000, Havalige, Thippeswamy wrote: > Hi Conor Dooley, > > > -----Original Message----- > > From: Conor Dooley <conor@kernel.org> > > Sent: Monday, July 22, 2024 10:15 PM > > To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com> > > Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; > > bhelgaas@google.com; krzk+dt@kernel.org; conor+dt@kernel.org; linux- > > kernel@vger.kernel.org; devicetree@vger.kernel.org; linux- > > pci@vger.kernel.org; Havalige, Thippeswamy > > <thippeswamy.havalige@amd.com>; linux-arm-kernel@lists.infradead.org; > > Simek, Michal <michal.simek@amd.com> > > Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for > > Xilinx QDMA PCIe Root Port Bridge > > > > On Mon, Jul 22, 2024 at 11:55:57AM +0530, Thippeswamy Havalige wrote: > > > Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port > > Bridge. > > > > > > Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> > > > --- > > > .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- > > > 1 file changed, 39 insertions(+), 2 deletions(-) > > > --- > > > changes in v2 > > > - update dt node label with pcie. > > > --- > > > diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > > index 2f59b3a73dd2..28d9350a7fb4 100644 > > > --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > > +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml > > > @@ -14,10 +14,21 @@ allOf: > > > > > > properties: > > > compatible: > > > - const: xlnx,xdma-host-3.00 > > > + enum: > > > + - xlnx,xdma-host-3.00 > > > + - xlnx,qdma-host-3.00 > > > > > > reg: > > > - maxItems: 1 > > > + items: > > > + - description: configuration region and XDMA bridge register. > > > + - description: QDMA bridge register. > > > > Please constrain the new entry to only the new compatible. > - Thanks, I ll resend patch with required changes. Weird quoting btw, the - isn't needed. > > > + minItems: 1 > > > + > > > + reg-names: > > > + items: > > > + - const: cfg > > > + - const: breg > > > + minItems: 1 > > > > > > ranges: > > > maxItems: 2 > > > @@ -111,4 +122,30 @@ examples: > > > interrupt-controller; > > > }; > > > }; > > > + > > > + pcie@80000000 { > > > > tbh, don't see the point of a new example for this. > - For this in both examples ranges properties are different. So, here I wanted to make sure that our example device tree bindings work straight forward when our reference designs are used. Different ranges properties doesn't justify a new example. They don't exist to be copy-pasted, but rather to demonstrate usage of properties and validate the binding.
diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 2f59b3a73dd2..28d9350a7fb4 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -14,10 +14,21 @@ allOf: properties: compatible: - const: xlnx,xdma-host-3.00 + enum: + - xlnx,xdma-host-3.00 + - xlnx,qdma-host-3.00 reg: - maxItems: 1 + items: + - description: configuration region and XDMA bridge register. + - description: QDMA bridge register. + minItems: 1 + + reg-names: + items: + - const: cfg + - const: breg + minItems: 1 ranges: maxItems: 2 @@ -111,4 +122,30 @@ examples: interrupt-controller; }; }; + + pcie@80000000 { + compatible = "xlnx,qdma-host-3.00"; + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>; + reg-names = "cfg", "breg"; + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; };
Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige <thippesw@amd.com> --- .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) --- changes in v2 - update dt node label with pcie. ---