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Tue, 16 Jul 2024 03:42:54 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 16 Jul 2024 03:42:54 -0500 Received: from localhost (uda0496377.dhcp.ti.com [172.24.227.31]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 46G8grPh118721; Tue, 16 Jul 2024 03:42:53 -0500 From: Aradhya Bhatia To: Tomi Valkeinen , Jyri Sarha , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Laurent Pinchart , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: DRI Development List , Devicetree List , Linux Kernel List , Nishanth Menon , Vignesh Raghavendra , Praneeth Bajjuri , Udit Kumar , Francesco Dolcini , Alexander Sverdlin , Randolph Sapp , Devarsh Thakkar , Jayesh Choudhary , Jai Luthra , Aradhya Bhatia Subject: [PATCH v3 3/4] dt-bindings: display: ti,am65x-dss: Add OLDI properties for AM625 DSS Date: Tue, 16 Jul 2024 14:12:47 +0530 Message-ID: <20240716084248.1393666-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240716084248.1393666-1-a-bhatia1@ti.com> References: <20240716084248.1393666-1-a-bhatia1@ti.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 The DSS in AM625 SoC has 2 OLDI TXes. Refer the OLDI schema to add the support for the OLDI TXes. The AM625 DSS VP1 (port@0) can connect and control 2 OLDI TXes, to use them in dual-link or cloned single-link OLDI modes. Add support for an additional endpoint under the port@0 to accurately depict the data flow path. Signed-off-by: Aradhya Bhatia --- .../bindings/display/ti/ti,am65x-dss.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 399d68986326..249597455d34 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -91,6 +91,24 @@ properties: For AM625 DSS, the internal DPI output port node from video port 1. For AM62A7 DSS, the port is tied off inside the SoC. + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: + For AM625 DSS, VP Connection to OLDI0. + For AM65X DSS, OLDI output from the SoC. + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: + For AM625 DSS, VP Connection to OLDI1. + + anyOf: + - required: + - endpoint + - required: + - endpoint@0 + - endpoint@1 port@1: $ref: /schemas/graph.yaml#/properties/port @@ -112,6 +130,23 @@ properties: Input memory (from main memory to dispc) bandwidth limit in bytes per second + oldi-txes: + type: object + additionalProperties: true + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^oldi_tx@[0-1]$': + type: object + $ref: ti,am625-oldi.yaml# + unevaluatedProperties: false + description: OLDI transmitters connected to the DSS VPs + allOf: - if: properties: @@ -123,6 +158,19 @@ allOf: ports: properties: port@0: false + oldi_txes: false + + - if: + properties: + compatible: + contains: + const: ti,am65x-dss + then: + properties: + oldi_txes: false + port@0: + properties: + endpoint@1: false required: - compatible @@ -171,3 +219,90 @@ examples: }; }; }; + + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + dss1: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1 */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2 */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2", "common1"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&vp1_clock>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = ; + oldi-txes { + #address-cells = <1>; + #size-cells = <0>; + oldi0: oldi@0 { + reg = <0>; + clocks = <&k3_clks 186 0>; + clock-names = "s_clk"; + ti,companion-oldi = <&oldi1>; + ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; + }; + }; + }; + oldi1: oldi@1 { + reg = <1>; + ti,secondary-oldi; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + oldi1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; + }; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi1_in>; + }; + }; + port@1 { + reg = <1>; + dpi1_out: endpoint { + remote-endpoint = <&hdmi_bridge>; + }; + }; + }; + }; + };