@@ -30,6 +30,26 @@ properties:
Clock controller node that provides the clocks controlled by the SCU
$ref: /schemas/clock/fsl,scu-clk.yaml
+ dc0-pixel-link0:
+ description:
+ Display pixel link0 in display controller subsystem0 controlled by the SCU
+ $ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+ dc0-pixel-link1:
+ description:
+ Display pixel link1 in display controller subsystem0 controlled by the SCU
+ $ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+ dc1-pixel-link0:
+ description:
+ Display pixel link0 in display controller subsystem1 controlled by the SCU
+ $ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
+ dc1-pixel-link1:
+ description:
+ Display pixel link1 in display controller subsystem1 controlled by the SCU
+ $ref: /schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml
+
gpio:
description:
Control the GPIO PINs on SCU domain over the firmware APIs
Document SCU controlled display pixel link child nodes. Signed-off-by: Liu Ying <victor.liu@nxp.com> --- v2: * New patch as needed by display controller subsystem device tree. .../devicetree/bindings/firmware/fsl,scu.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+)