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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717758883; bh=0ArQlCvHIIXLagRFXrfsGxVZ7s8NLv5FvY16U5TNFcc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EjWK+86C+IwPuNGJ7G+aL7euUVjHMwR59DX3jnJpNUG1O/hTyiGLWMU+MeC8Hpwil AM0JYpXAqtXeEGrmvwnWfDzAiSwoUgnQg1UgyVGpMOKbSCN0V0FDzew4SugzySNxdl sUaEXbg0zmZBQb2Z6Gxf4lHu2ovz2lQRSHjEBYVeqKPbkS1/lt7nY3VK8KQT1eEKSy n71rCrI6fc36H47rYeot953Yjhg9Prx8KsBgXw+c+oei1oTd3VD9QegrVHNONiVofD oSTcgspYBGNBpE6sjv3tp+5W9LtGfoAhwbNcdknj8vYhyo2mtz/tatQGkVCJv1t5DN QIBjfcwC/hA3A== From: Niklas Cassel Date: Fri, 07 Jun 2024 13:14:23 +0200 Subject: [PATCH v5 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240607-rockchip-pcie-ep-v1-v5-3-0a042d6b0049@kernel.org> References: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> In-Reply-To: <20240607-rockchip-pcie-ep-v1-v5-0-0a042d6b0049@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1743; i=cassel@kernel.org; h=from:subject:message-id; bh=0ArQlCvHIIXLagRFXrfsGxVZ7s8NLv5FvY16U5TNFcc=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNKSXk+sbPnG7ZJUeUrxxCWWArn4Vy5lczRk5j3WfJKyY 01Of8jPjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEzk3WJGhmkBL7V+iqUvfhIv KPmm88ZKz68t5ev+Zm2c/MEn+lu84gqGf+p8/1MnyVxW7mzhOJLU67/mmeXr78ZXX8g8FA5f8sw 8hBcA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings.