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Wed, 03 Apr 2024 10:42:41 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 433AgeYo027472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Apr 2024 10:42:40 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 3 Apr 2024 03:42:36 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v7 1/5] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Date: Wed, 3 Apr 2024 16:12:16 +0530 Message-ID: <20240403104220.1092431-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240403104220.1092431-1-quic_varada@quicinc.com> References: <20240403104220.1092431-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: g3AfaEDS0rL7jAjVcPdQ0zLAKpPoxMts X-Proofpoint-ORIG-GUID: g3AfaEDS0rL7jAjVcPdQ0zLAKpPoxMts X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-03_09,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404030074 Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework. Signed-off-by: Varadarajan Narayanan --- v7: Fix macro names to be consistent with other bindings v6: Removed Reviewed-by: Krzysztof Kozlowski Redefine the bindings such that driver and DT can share them v3: Squash Documentation/ and include/ changes into same patch qcom,ipq9574.h Move 'first id' to clock driver --- .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 + .../dt-bindings/interconnect/qcom,ipq9574.h | 87 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h new file mode 100644 index 000000000000..0b076b0cf880 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ9574_H +#define INTERCONNECT_QCOM_IPQ9574_H + +#define ICC_ANOC_PCIE0 0 +#define ICC_SNOC_PCIE0 1 +#define ICC_ANOC_PCIE1 2 +#define ICC_SNOC_PCIE1 3 +#define ICC_ANOC_PCIE2 4 +#define ICC_SNOC_PCIE2 5 +#define ICC_ANOC_PCIE3 6 +#define ICC_SNOC_PCIE3 7 +#define ICC_SNOC_USB 8 +#define ICC_ANOC_USB_AXI 9 +#define ICC_NSSNOC_NSSCC 10 +#define ICC_NSSNOC_SNOC_0 11 +#define ICC_NSSNOC_SNOC_1 12 +#define ICC_NSSNOC_PCNOC_1 13 +#define ICC_NSSNOC_QOSGEN_REF 14 +#define ICC_NSSNOC_TIMEOUT_REF 15 +#define ICC_NSSNOC_XO_DCD 16 +#define ICC_NSSNOC_ATB 17 +#define ICC_MEM_NOC_NSSNOC 18 +#define ICC_NSSNOC_MEMNOC 19 +#define ICC_NSSNOC_MEM_NOC_1 20 + +#define ICC_NSSNOC_PPE 0 +#define ICC_NSSNOC_PPE_CFG 1 +#define ICC_NSSNOC_NSS_CSR 2 +#define ICC_NSSNOC_IMEM_QSB 3 +#define ICC_NSSNOC_IMEM_AHB 4 + +#define MASTER_ANOC_PCIE0 (ICC_ANOC_PCIE0 * 2) +#define SLAVE_ANOC_PCIE0 ((ICC_ANOC_PCIE0 * 2) + 1) +#define MASTER_SNOC_PCIE0 (ICC_SNOC_PCIE0 * 2) +#define SLAVE_SNOC_PCIE0 ((ICC_SNOC_PCIE0 * 2) + 1) +#define MASTER_ANOC_PCIE1 (ICC_ANOC_PCIE1 * 2) +#define SLAVE_ANOC_PCIE1 ((ICC_ANOC_PCIE1 * 2) + 1) +#define MASTER_SNOC_PCIE1 (ICC_SNOC_PCIE1 * 2) +#define SLAVE_SNOC_PCIE1 ((ICC_SNOC_PCIE1 * 2) + 1) +#define MASTER_ANOC_PCIE2 (ICC_ANOC_PCIE2 * 2) +#define SLAVE_ANOC_PCIE2 ((ICC_ANOC_PCIE2 * 2) + 1) +#define MASTER_SNOC_PCIE2 (ICC_SNOC_PCIE2 * 2) +#define SLAVE_SNOC_PCIE2 ((ICC_SNOC_PCIE2 * 2) + 1) +#define MASTER_ANOC_PCIE3 (ICC_ANOC_PCIE3 * 2) +#define SLAVE_ANOC_PCIE3 ((ICC_ANOC_PCIE3 * 2) + 1) +#define MASTER_SNOC_PCIE3 (ICC_SNOC_PCIE3 * 2) +#define SLAVE_SNOC_PCIE3 ((ICC_SNOC_PCIE3 * 2) + 1) +#define MASTER_USB (ICC_USB * 2) +#define SLAVE_USB ((ICC_USB * 2) + 1) +#define MASTER_USB_AXI (ICC_USB_AXI * 2) +#define SLAVE_USB_AXI ((ICC_USB_AXI * 2) + 1) +#define MASTER_NSSNOC_NSSCC (ICC_NSSNOC_NSSCC * 2) +#define SLAVE_NSSNOC_NSSCC ((ICC_NSSNOC_NSSCC * 2) + 1) +#define MASTER_NSSNOC_SNOC_0 (ICC_NSSNOC_SNOC_0 * 2) +#define SLAVE_NSSNOC_SNOC_0 ((ICC_NSSNOC_SNOC_0 * 2) + 1) +#define MASTER_NSSNOC_SNOC_1 (ICC_NSSNOC_SNOC_1 * 2) +#define SLAVE_NSSNOC_SNOC_1 ((ICC_NSSNOC_SNOC_1 * 2) + 1) +#define MASTER_NSSNOC_PCNOC_1 (ICC_NSSNOC_PCNOC_1 * 2) +#define SLAVE_NSSNOC_PCNOC_1 ((ICC_NSSNOC_PCNOC_1 * 2) + 1) +#define MASTER_NSSNOC_QOSGEN_REF (ICC_NSSNOC_QOSGEN_REF * 2) +#define SLAVE_NSSNOC_QOSGEN_REF ((ICC_NSSNOC_QOSGEN_REF * 2) + 1) +#define MASTER_NSSNOC_TIMEOUT_REF (ICC_NSSNOC_TIMEOUT_REF * 2) +#define SLAVE_NSSNOC_TIMEOUT_REF ((ICC_NSSNOC_TIMEOUT_REF * 2) + 1) +#define MASTER_NSSNOC_XO_DCD (ICC_NSSNOC_XO_DCD * 2) +#define SLAVE_NSSNOC_XO_DCD ((ICC_NSSNOC_XO_DCD * 2) + 1) +#define MASTER_NSSNOC_ATB (ICC_NSSNOC_ATB * 2) +#define SLAVE_NSSNOC_ATB ((ICC_NSSNOC_ATB * 2) + 1) +#define MASTER_MEM_NOC_NSSNOC (ICC_MEM_NOC_NSSNOC * 2) +#define SLAVE_MEM_NOC_NSSNOC ((ICC_MEM_NOC_NSSNOC * 2) + 1) +#define MASTER_NSSNOC_MEMNOC (ICC_NSSNOC_MEMNOC * 2) +#define SLAVE_NSSNOC_MEMNOC ((ICC_NSSNOC_MEMNOC * 2) + 1) +#define MASTER_NSSNOC_MEM_NOC_1 (ICC_NSSNOC_MEM_NOC_1 * 2) +#define SLAVE_NSSNOC_MEM_NOC_1 ((ICC_NSSNOC_MEM_NOC_1 * 2) + 1) + +#define MASTER_NSSNOC_PPE (ICC_NSSNOC_PPE * 2) +#define SLAVE_NSSNOC_PPE ((ICC_NSSNOC_PPE * 2) + 1) +#define MASTER_NSSNOC_PPE_CFG (ICC_NSSNOC_PPE_CFG * 2) +#define SLAVE_NSSNOC_PPE_CFG ((ICC_NSSNOC_PPE_CFG * 2) + 1) +#define MASTER_NSSNOC_NSS_CSR (ICC_NSSNOC_NSS_CSR * 2) +#define SLAVE_NSSNOC_NSS_CSR ((ICC_NSSNOC_NSS_CSR * 2) + 1) +#define MASTER_NSSNOC_IMEM_QSB (ICC_NSSNOC_IMEM_QSB * 2) +#define SLAVE_NSSNOC_IMEM_QSB ((ICC_NSSNOC_IMEM_QSB * 2) + 1) +#define MASTER_NSSNOC_IMEM_AHB (ICC_NSSNOC_IMEM_AHB * 2) +#define SLAVE_NSSNOC_IMEM_AHB ((ICC_NSSNOC_IMEM_AHB * 2) + 1) + +#endif /* INTERCONNECT_QCOM_IPQ9574_H */