| Message ID | 20240315095555.2628684-1-xu.yang_2@nxp.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v7,1/8] dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Fri, Mar 15, 2024 at 05:55:54PM +0800, Xu Yang wrote: > Add JSON metrics for i.MX95 DDR Performance Monitor. > > Reviewed-by: John Garry <john.g.garry@oracle.com> > Reviewed-by: Ian Rogers <irogers@google.com> > Reviewed-by: Frank Li <Frank.Li@nxp.com> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> I'm applying the tools/perf/ patches, that is 7/8 and 8/8, but I noticed that 8/8 has no Reviewed-by tags, is that really the case? If so, can we have them? - Arnaldo > --- > Changes in v2: > - fix wrong AXI_MASK setting > - remove unnecessary metrics > - add bandwidth_usage, camera_all, disp_all metrics > Changes in v3: > - no changes > Changes in v4: > - add Reviewed-by tag > Changes in v5: > - fix typo > Changes in v6: > - remove "counter=X" from each metric > Changes in v7: > - add RB tag > --- > .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + > .../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++ > tools/perf/pmu-events/jevents.py | 1 + > 3 files changed, 788 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > new file mode 100644 > index 000000000000..4dc9d2968bdc > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > @@ -0,0 +1,9 @@ > +[ > + { > + "BriefDescription": "ddr cycles event", > + "EventCode": "0x00", > + "EventName": "imx95_ddr.cycles", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + } > +] > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > new file mode 100644 > index 000000000000..a3ae787d448c > --- /dev/null > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > @@ -0,0 +1,778 @@ > +[ > + { > + "BriefDescription": "bandwidth usage for lpddr5 evk board", > + "MetricName": "imx95_bandwidth_usage.lpddr5", > + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)", > + "ScaleUnit": "1e2%", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all masters read from ddr", > + "MetricName": "imx95_ddr_read.all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all masters write to ddr", > + "MetricName": "imx95_ddr_write.all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all a55 read from ddr", > + "MetricName": "imx95_ddr_read.a55_all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all a55 write to ddr (part1)", > + "MetricName": "imx95_ddr_write.a55_all_1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all a55 write to ddr (part2)", > + "MetricName": "imx95_ddr_write.a55_all_2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 0 read from ddr", > + "MetricName": "imx95_ddr_read.a55_0", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 0 write to ddr", > + "MetricName": "imx95_ddr_write.a55_0", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 1 read from ddr", > + "MetricName": "imx95_ddr_read.a55_1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 1 write to ddr", > + "MetricName": "imx95_ddr_write.a55_1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 2 read from ddr", > + "MetricName": "imx95_ddr_read.a55_2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 2 write to ddr", > + "MetricName": "imx95_ddr_write.a55_2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 3 read from ddr", > + "MetricName": "imx95_ddr_read.a55_3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 3 write to ddr", > + "MetricName": "imx95_ddr_write.a55_3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 4 read from ddr", > + "MetricName": "imx95_ddr_read.a55_4", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 4 write to ddr", > + "MetricName": "imx95_ddr_write.a55_4", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 5 read from ddr", > + "MetricName": "imx95_ddr_read.a55_5", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of a55 core 5 write to ddr", > + "MetricName": "imx95_ddr_write.a55_5", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", > + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", > + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of m33 read from ddr", > + "MetricName": "imx95_ddr_read.m33", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of m33 write to ddr", > + "MetricName": "imx95_ddr_write.m33", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of m7 read from ddr", > + "MetricName": "imx95_ddr_read.m7", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of m7 write to ddr", > + "MetricName": "imx95_ddr_write.m7", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of sentinel read from ddr", > + "MetricName": "imx95_ddr_read.sentinel", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of sentinel write to ddr", > + "MetricName": "imx95_ddr_write.sentinel", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of edma1 read from ddr", > + "MetricName": "imx95_ddr_read.edma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of edma1 write to ddr", > + "MetricName": "imx95_ddr_write.edma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of edma2 read from ddr", > + "MetricName": "imx95_ddr_read.edma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of edma2 write to ddr", > + "MetricName": "imx95_ddr_write.edma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of netc read from ddr", > + "MetricName": "imx95_ddr_read.netc", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of netc write to ddr", > + "MetricName": "imx95_ddr_write.netc", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of npu read from ddr", > + "MetricName": "imx95_ddr_read.npu", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of npu write to ddr", > + "MetricName": "imx95_ddr_write.npu", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of gpu read from ddr", > + "MetricName": "imx95_ddr_read.gpu", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of gpu write to ddr", > + "MetricName": "imx95_ddr_write.gpu", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc1 read from ddr", > + "MetricName": "imx95_ddr_read.usdhc1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc1 write to ddr", > + "MetricName": "imx95_ddr_write.usdhc1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc2 read from ddr", > + "MetricName": "imx95_ddr_read.usdhc2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc2 write to ddr", > + "MetricName": "imx95_ddr_write.usdhc2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc3 read from ddr", > + "MetricName": "imx95_ddr_read.usdhc3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usdhc3 write to ddr", > + "MetricName": "imx95_ddr_write.usdhc3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of xspi read from ddr", > + "MetricName": "imx95_ddr_read.xspi", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of xspi write to ddr", > + "MetricName": "imx95_ddr_write.xspi", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie1 read from ddr", > + "MetricName": "imx95_ddr_read.pcie1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie1 write to ddr", > + "MetricName": "imx95_ddr_write.pcie1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie2 read from ddr", > + "MetricName": "imx95_ddr_read.pcie2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie2 write to ddr", > + "MetricName": "imx95_ddr_write.pcie2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie3 read from ddr", > + "MetricName": "imx95_ddr_read.pcie3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie3 write to ddr", > + "MetricName": "imx95_ddr_write.pcie3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie4 read from ddr", > + "MetricName": "imx95_ddr_read.pcie4", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of pcie4 write to ddr", > + "MetricName": "imx95_ddr_write.pcie4", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usb1 read from ddr", > + "MetricName": "imx95_ddr_read.usb1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usb1 write to ddr", > + "MetricName": "imx95_ddr_write.usb1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usb2 read from ddr", > + "MetricName": "imx95_ddr_read.usb2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of usb2 write to ddr", > + "MetricName": "imx95_ddr_write.usb2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of vpu codec primary bus read from ddr", > + "MetricName": "imx95_ddr_read.vpu_primy", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of vpu codec primary bus write to ddr", > + "MetricName": "imx95_ddr_write.vpu_primy", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", > + "MetricName": "imx95_ddr_read.vpu_secndy", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", > + "MetricName": "imx95_ddr_write.vpu_secndy", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of jpeg decoder read from ddr", > + "MetricName": "imx95_ddr_read.jpeg_dec", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of jpeg decoder write to ddr", > + "MetricName": "imx95_ddr_write.jpeg_dec", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of jpeg encoder read from ddr", > + "MetricName": "imx95_ddr_read.jpeg_dec", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of jpeg encoder write to ddr", > + "MetricName": "imx95_ddr_write.jpeg_enc", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all vpu submodules read from ddr", > + "MetricName": "imx95_ddr_read.vpu_all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all vpu submodules write to ddr", > + "MetricName": "imx95_ddr_write.vpu_all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of cortex m0+ read from ddr", > + "MetricName": "imx95_ddr_read.m0", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of cortex m0+ write to ddr", > + "MetricName": "imx95_ddr_write.m0", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of camera edma read from ddr", > + "MetricName": "imx95_ddr_read.camera_edma", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of camera edma write to ddr", > + "MetricName": "imx95_ddr_write.camera_edma", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi rd read from ddr", > + "MetricName": "imx95_ddr_read.isi_rd", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi rd write to ddr", > + "MetricName": "imx95_ddr_write.isi_rd", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr y read from ddr", > + "MetricName": "imx95_ddr_read.isi_wr_y", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr y write to ddr", > + "MetricName": "imx95_ddr_write.isi_wr_y", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr u read from ddr", > + "MetricName": "imx95_ddr_read.isi_wr_u", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr u write to ddr", > + "MetricName": "imx95_ddr_write.isi_wr_u", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr v read from ddr", > + "MetricName": "imx95_ddr_read.isi_wr_v", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isi wr v write to ddr", > + "MetricName": "imx95_ddr_write.isi_wr_v", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp input dma1 read from ddr", > + "MetricName": "imx95_ddr_read.isp_in_dma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp input dma1 write to ddr", > + "MetricName": "imx95_ddr_write.isp_in_dma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp input dma2 read from ddr", > + "MetricName": "imx95_ddr_read.isp_in_dma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp input dma2 write to ddr", > + "MetricName": "imx95_ddr_write.isp_in_dma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp output dma1 read from ddr", > + "MetricName": "imx95_ddr_read.isp_out_dma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp output dma1 write to ddr", > + "MetricName": "imx95_ddr_write.isp_out_dma1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp output dma2 read from ddr", > + "MetricName": "imx95_ddr_read.isp_out_dma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of isp output dma2 write to ddr", > + "MetricName": "imx95_ddr_write.isp_out_dma2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all camera submodules read from ddr", > + "MetricName": "imx95_ddr_read.camera_all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", > + "MetricName": "imx95_ddr_write.camera_all_1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", > + "MetricName": "imx95_ddr_write.camera_all_2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", > + "MetricName": "imx95_ddr_write.camera_all_3", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of display blitter store read from ddr", > + "MetricName": "imx95_ddr_read.disp_blit", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of display blitter write to ddr", > + "MetricName": "imx95_ddr_write.disp_blit", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of display command sequencer read from ddr", > + "MetricName": "imx95_ddr_read.disp_cmd", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of display command sequencer write to ddr", > + "MetricName": "imx95_ddr_write.disp_cmd", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all display submodules read from ddr", > + "MetricName": "imx95_ddr_read.disp_all", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all display submodules write to ddr (part1)", > + "MetricName": "imx95_ddr_write.disp_all_1", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + }, > + { > + "BriefDescription": "bytes of all display submodules write to ddr (part2)", > + "MetricName": "imx95_ddr_write.disp_all_2", > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > + "ScaleUnit": "9.765625e-4KB", > + "Unit": "imx9_ddr", > + "Compat": "imx95" > + } > +] > diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py > index 53ab050c8fa4..be4b541a0820 100755 > --- a/tools/perf/pmu-events/jevents.py > +++ b/tools/perf/pmu-events/jevents.py > @@ -284,6 +284,7 @@ class JsonEvent: > 'hisi_sccl,hha': 'hisi_sccl,hha', > 'hisi_sccl,l3c': 'hisi_sccl,l3c', > 'imx8_ddr': 'imx8_ddr', > + 'imx9_ddr': 'imx9_ddr', > 'L3PMC': 'amd_l3', > 'DFPMC': 'amd_df', > 'UMCPMC': 'amd_umc', > -- > 2.34.1
Hi Arnaldo, > > On Fri, Mar 15, 2024 at 05:55:54PM +0800, Xu Yang wrote: > > Add JSON metrics for i.MX95 DDR Performance Monitor. > > > > Reviewed-by: John Garry <john.g.garry@oracle.com> > > Reviewed-by: Ian Rogers <irogers@google.com> > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > I'm applying the tools/perf/ patches, that is 7/8 and 8/8, but I noticed > that 8/8 has no Reviewed-by tags, is that really the case? If so, can we > have them? I found IMX93 metrics are still not added until v6, then I add patch 8/8 in v7. So it's still waiting for review I think. Sorry for inconvenience. Thanks, Xu Yang > > - Arnaldo > > > --- > > Changes in v2: > > - fix wrong AXI_MASK setting > > - remove unnecessary metrics > > - add bandwidth_usage, camera_all, disp_all metrics > > Changes in v3: > > - no changes > > Changes in v4: > > - add Reviewed-by tag > > Changes in v5: > > - fix typo > > Changes in v6: > > - remove "counter=X" from each metric > > Changes in v7: > > - add RB tag > > --- > > .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + > > .../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++ > > tools/perf/pmu-events/jevents.py | 1 + > > 3 files changed, 788 insertions(+) > > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > > > > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu- > events/arch/arm64/freescale/imx95/sys/ddrc.json > > new file mode 100644 > > index 000000000000..4dc9d2968bdc > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > > @@ -0,0 +1,9 @@ > > +[ > > + { > > + "BriefDescription": "ddr cycles event", > > + "EventCode": "0x00", > > + "EventName": "imx95_ddr.cycles", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + } > > +] > > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu- > events/arch/arm64/freescale/imx95/sys/metrics.json > > new file mode 100644 > > index 000000000000..a3ae787d448c > > --- /dev/null > > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > > @@ -0,0 +1,778 @@ > > +[ > > + { > > + "BriefDescription": "bandwidth usage for lpddr5 evk board", > > + "MetricName": "imx95_bandwidth_usage.lpddr5", > > + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + > imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * > 4)", > > + "ScaleUnit": "1e2%", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all masters read from ddr", > > + "MetricName": "imx95_ddr_read.all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all masters write to ddr", > > + "MetricName": "imx95_ddr_write.all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all a55 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all a55 write to ddr (part1)", > > + "MetricName": "imx95_ddr_write.a55_all_1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all a55 write to ddr (part2)", > > + "MetricName": "imx95_ddr_write.a55_all_2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 0 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_0", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 0 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_0", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 1 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 1 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 2 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 2 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 3 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 3 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 4 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_4", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 4 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_4", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 5 read from ddr", > > + "MetricName": "imx95_ddr_read.a55_5", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of a55 core 5 write to ddr", > > + "MetricName": "imx95_ddr_write.a55_5", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", > > + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", > > + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of m33 read from ddr", > > + "MetricName": "imx95_ddr_read.m33", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of m33 write to ddr", > > + "MetricName": "imx95_ddr_write.m33", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of m7 read from ddr", > > + "MetricName": "imx95_ddr_read.m7", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of m7 write to ddr", > > + "MetricName": "imx95_ddr_write.m7", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of sentinel read from ddr", > > + "MetricName": "imx95_ddr_read.sentinel", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of sentinel write to ddr", > > + "MetricName": "imx95_ddr_write.sentinel", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of edma1 read from ddr", > > + "MetricName": "imx95_ddr_read.edma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of edma1 write to ddr", > > + "MetricName": "imx95_ddr_write.edma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of edma2 read from ddr", > > + "MetricName": "imx95_ddr_read.edma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of edma2 write to ddr", > > + "MetricName": "imx95_ddr_write.edma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of netc read from ddr", > > + "MetricName": "imx95_ddr_read.netc", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of netc write to ddr", > > + "MetricName": "imx95_ddr_write.netc", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of npu read from ddr", > > + "MetricName": "imx95_ddr_read.npu", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of npu write to ddr", > > + "MetricName": "imx95_ddr_write.npu", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of gpu read from ddr", > > + "MetricName": "imx95_ddr_read.gpu", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of gpu write to ddr", > > + "MetricName": "imx95_ddr_write.gpu", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc1 read from ddr", > > + "MetricName": "imx95_ddr_read.usdhc1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc1 write to ddr", > > + "MetricName": "imx95_ddr_write.usdhc1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc2 read from ddr", > > + "MetricName": "imx95_ddr_read.usdhc2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc2 write to ddr", > > + "MetricName": "imx95_ddr_write.usdhc2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc3 read from ddr", > > + "MetricName": "imx95_ddr_read.usdhc3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usdhc3 write to ddr", > > + "MetricName": "imx95_ddr_write.usdhc3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of xspi read from ddr", > > + "MetricName": "imx95_ddr_read.xspi", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of xspi write to ddr", > > + "MetricName": "imx95_ddr_write.xspi", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie1 read from ddr", > > + "MetricName": "imx95_ddr_read.pcie1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie1 write to ddr", > > + "MetricName": "imx95_ddr_write.pcie1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie2 read from ddr", > > + "MetricName": "imx95_ddr_read.pcie2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie2 write to ddr", > > + "MetricName": "imx95_ddr_write.pcie2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie3 read from ddr", > > + "MetricName": "imx95_ddr_read.pcie3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie3 write to ddr", > > + "MetricName": "imx95_ddr_write.pcie3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie4 read from ddr", > > + "MetricName": "imx95_ddr_read.pcie4", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of pcie4 write to ddr", > > + "MetricName": "imx95_ddr_write.pcie4", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usb1 read from ddr", > > + "MetricName": "imx95_ddr_read.usb1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usb1 write to ddr", > > + "MetricName": "imx95_ddr_write.usb1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usb2 read from ddr", > > + "MetricName": "imx95_ddr_read.usb2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of usb2 write to ddr", > > + "MetricName": "imx95_ddr_write.usb2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of vpu codec primary bus read from ddr", > > + "MetricName": "imx95_ddr_read.vpu_primy", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of vpu codec primary bus write to ddr", > > + "MetricName": "imx95_ddr_write.vpu_primy", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", > > + "MetricName": "imx95_ddr_read.vpu_secndy", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", > > + "MetricName": "imx95_ddr_write.vpu_secndy", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of jpeg decoder read from ddr", > > + "MetricName": "imx95_ddr_read.jpeg_dec", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of jpeg decoder write to ddr", > > + "MetricName": "imx95_ddr_write.jpeg_dec", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of jpeg encoder read from ddr", > > + "MetricName": "imx95_ddr_read.jpeg_dec", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of jpeg encoder write to ddr", > > + "MetricName": "imx95_ddr_write.jpeg_enc", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all vpu submodules read from ddr", > > + "MetricName": "imx95_ddr_read.vpu_all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all vpu submodules write to ddr", > > + "MetricName": "imx95_ddr_write.vpu_all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of cortex m0+ read from ddr", > > + "MetricName": "imx95_ddr_read.m0", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of cortex m0+ write to ddr", > > + "MetricName": "imx95_ddr_write.m0", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of camera edma read from ddr", > > + "MetricName": "imx95_ddr_read.camera_edma", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of camera edma write to ddr", > > + "MetricName": "imx95_ddr_write.camera_edma", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi rd read from ddr", > > + "MetricName": "imx95_ddr_read.isi_rd", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi rd write to ddr", > > + "MetricName": "imx95_ddr_write.isi_rd", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr y read from ddr", > > + "MetricName": "imx95_ddr_read.isi_wr_y", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr y write to ddr", > > + "MetricName": "imx95_ddr_write.isi_wr_y", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr u read from ddr", > > + "MetricName": "imx95_ddr_read.isi_wr_u", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr u write to ddr", > > + "MetricName": "imx95_ddr_write.isi_wr_u", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr v read from ddr", > > + "MetricName": "imx95_ddr_read.isi_wr_v", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isi wr v write to ddr", > > + "MetricName": "imx95_ddr_write.isi_wr_v", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp input dma1 read from ddr", > > + "MetricName": "imx95_ddr_read.isp_in_dma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp input dma1 write to ddr", > > + "MetricName": "imx95_ddr_write.isp_in_dma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp input dma2 read from ddr", > > + "MetricName": "imx95_ddr_read.isp_in_dma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp input dma2 write to ddr", > > + "MetricName": "imx95_ddr_write.isp_in_dma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp output dma1 read from ddr", > > + "MetricName": "imx95_ddr_read.isp_out_dma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp output dma1 write to ddr", > > + "MetricName": "imx95_ddr_write.isp_out_dma1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp output dma2 read from ddr", > > + "MetricName": "imx95_ddr_read.isp_out_dma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of isp output dma2 write to ddr", > > + "MetricName": "imx95_ddr_write.isp_out_dma2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all camera submodules read from ddr", > > + "MetricName": "imx95_ddr_read.camera_all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + > imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", > > + "MetricName": "imx95_ddr_write.camera_all_1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", > > + "MetricName": "imx95_ddr_write.camera_all_2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", > > + "MetricName": "imx95_ddr_write.camera_all_3", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of display blitter store read from ddr", > > + "MetricName": "imx95_ddr_read.disp_blit", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of display blitter write to ddr", > > + "MetricName": "imx95_ddr_write.disp_blit", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of display command sequencer read from ddr", > > + "MetricName": "imx95_ddr_read.disp_cmd", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of display command sequencer write to ddr", > > + "MetricName": "imx95_ddr_write.disp_cmd", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all display submodules read from ddr", > > + "MetricName": "imx95_ddr_read.disp_all", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all display submodules write to ddr (part1)", > > + "MetricName": "imx95_ddr_write.disp_all_1", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + }, > > + { > > + "BriefDescription": "bytes of all display submodules write to ddr (part2)", > > + "MetricName": "imx95_ddr_write.disp_all_2", > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > > + "ScaleUnit": "9.765625e-4KB", > > + "Unit": "imx9_ddr", > > + "Compat": "imx95" > > + } > > +] > > diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py > > index 53ab050c8fa4..be4b541a0820 100755 > > --- a/tools/perf/pmu-events/jevents.py > > +++ b/tools/perf/pmu-events/jevents.py > > @@ -284,6 +284,7 @@ class JsonEvent: > > 'hisi_sccl,hha': 'hisi_sccl,hha', > > 'hisi_sccl,l3c': 'hisi_sccl,l3c', > > 'imx8_ddr': 'imx8_ddr', > > + 'imx9_ddr': 'imx9_ddr', > > 'L3PMC': 'amd_l3', > > 'DFPMC': 'amd_df', > > 'UMCPMC': 'amd_umc', > > -- > > 2.34.1
On Fri, Mar 15, 2024 at 05:55:49PM +0800, Xu Yang wrote: > The user can set event and counter in cmdline and the driver need to parse > it using 'config' attr value. This will add macro definitions to avoid > hard-code in driver. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > > --- > Changes in v4: > - new patch > Changes in v5: > - move this patch earlier > Changes in v6: > - no changes > Changes in v7: > - use FIELD_* > --- > drivers/perf/fsl_imx9_ddr_perf.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > index 9685645bfe04..4ec70775d1f0 100644 > --- a/drivers/perf/fsl_imx9_ddr_perf.c > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > @@ -42,6 +42,9 @@ > #define NUM_COUNTERS 11 > #define CYCLES_COUNTER 0 > > +#define CONFIG_EVENT GENMASK(7, 0) > +#define CONFIG_COUNTER GENMASK(15, 8) > + > #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) > > #define DDR_PERF_DEV_NAME "imx9_ddr" > @@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, > int counter, bool enable) > { > u32 ctrl_a; > + int event; > > ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); > + event = FIELD_GET(CONFIG_EVENT, config); > > if (enable) { > ctrl_a |= PMLCA_FC; > @@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, > ctrl_a &= ~PMLCA_FC; > ctrl_a |= PMLCA_CE; > ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); > - ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); > + ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); > writel(ctrl_a, pmu->base + PMLCA(counter)); > } else { > /* Freeze counter. */ > @@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int > u32 pmcfg1, pmcfg2; > int event, counter; > > - event = cfg & 0x000000FF; > - counter = (cfg & 0x0000FF00) >> 8; > + event = FIELD_GET(CONFIG_EVENT, cfg); > + counter = FIELD_GET(CONFIG_COUNTER, cfg); > > pmcfg1 = readl_relaxed(pmu->base + PMCFG1); > > @@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > int cfg2 = event->attr.config2; > int counter; > > - counter = (cfg & 0x0000FF00) >> 8; > + counter = FIELD_GET(CONFIG_COUNTER, cfg); > > pmu->events[counter] = event; > pmu->active_events++; > -- > 2.34.1 >
On Fri, Mar 15, 2024 at 05:55:50PM +0800, Xu Yang wrote: > In current design, the user of perf app needs to input counter ID to count > events. However, this is not user-friendly since the user needs to lookup > the map table to find the counter. Instead of letting the user to input > the counter, let this driver to manage the counters in this patch. > > This will be implemented by: > 1. allocate counter 0 for cycle event. > 2. find unused counter from 1-10 for reference events. > 3. allocate specific counter for counter-specific events. > > In this patch, counter attribute is removed too. To mark counter-specific > events, counter ID will be encoded into perf_pmu_events_attr.id. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > > --- > Changes in v6: > - new patch > Changes in v7: > - no changes > --- > drivers/perf/fsl_imx9_ddr_perf.c | 168 ++++++++++++++++++------------- > 1 file changed, 99 insertions(+), 69 deletions(-) > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > index 4ec70775d1f0..4fdf8bcf6646 100644 > --- a/drivers/perf/fsl_imx9_ddr_perf.c > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > @@ -41,9 +41,11 @@ > > #define NUM_COUNTERS 11 > #define CYCLES_COUNTER 0 > +#define CYCLES_EVENT_ID 0 > > #define CONFIG_EVENT GENMASK(7, 0) > #define CONFIG_COUNTER GENMASK(15, 8) > +#define CONFIG_COUNTER_OFFSET 8 > > #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) > > @@ -130,6 +132,8 @@ static ssize_t ddr_pmu_event_show(struct device *dev, > return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); > } > > +#define ID(counter, id) ((counter << CONFIG_COUNTER_OFFSET) | id) > + > #define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \ > (&((struct perf_pmu_events_attr[]) { \ > { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ > @@ -162,81 +166,81 @@ static struct attribute *ddr_perf_events_attrs[] = { > IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63), > > /* counter1 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, 66), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, 67), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, 68), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, 69), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, 70), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, 71), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)), > > /* counter2 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, 66), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, 67), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, 68), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, 69), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), > > /* counter3 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, 66), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, 67), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, 68), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, 69), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), > > /* counter4 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, 66), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, 67), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, 68), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, 69), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), > > /* counter5 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, 66), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, 67), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, 68), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, 69), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70), > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)), > > /* counter6 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, 72), > + IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)), > > /* counter7 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, 64), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, 65), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)), > > /* counter8 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, 64), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, 65), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)), > > /* counter9 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, 65), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, 66), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)), > > /* counter10 specific events */ > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, 65), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, 66), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)), > NULL, > }; > > @@ -245,14 +249,12 @@ static const struct attribute_group ddr_perf_events_attr_group = { > .attrs = ddr_perf_events_attrs, > }; > > -PMU_FORMAT_ATTR(event, "config:0-7"); > -PMU_FORMAT_ATTR(counter, "config:8-15"); > +PMU_FORMAT_ATTR(event, "config:0-15"); > PMU_FORMAT_ATTR(axi_id, "config1:0-17"); > PMU_FORMAT_ATTR(axi_mask, "config2:0-17"); > > static struct attribute *ddr_perf_format_attrs[] = { > &format_attr_event.attr, > - &format_attr_counter.attr, > &format_attr_axi_id.attr, > &format_attr_axi_mask.attr, > NULL, > @@ -366,13 +368,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, > } > } > > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) > +static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, > + int counter, int axi_id, int axi_mask) > { > u32 pmcfg1, pmcfg2; > - int event, counter; > - > - event = FIELD_GET(CONFIG_EVENT, cfg); > - counter = FIELD_GET(CONFIG_COUNTER, cfg); > > pmcfg1 = readl_relaxed(pmu->base + PMCFG1); > > @@ -392,12 +391,12 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int > pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; > > pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); > - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2); > + pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); > writel(pmcfg1, pmu->base + PMCFG1); > > pmcfg2 = readl_relaxed(pmu->base + PMCFG2); > pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); > - pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1); > + pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id); > writel(pmcfg2, pmu->base + PMCFG2); > } > > @@ -465,6 +464,28 @@ static void ddr_perf_event_start(struct perf_event *event, int flags) > hwc->state = 0; > } > > +static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter) > +{ > + int i; > + > + if (event == CYCLES_EVENT_ID) { > + // Cycles counter is dedicated for cycle event. > + if (pmu->events[CYCLES_COUNTER] == NULL) > + return CYCLES_COUNTER; > + } else if (counter != 0) { > + // Counter specific event use specific counter. > + if (pmu->events[counter] == NULL) > + return counter; > + } else { > + // Auto allocate counter for referene event. > + for (i = 1; i < NUM_COUNTERS; i++) > + if (pmu->events[i] == NULL) > + return i; > + } > + > + return -ENOENT; > +} > + > static int ddr_perf_event_add(struct perf_event *event, int flags) > { > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); > @@ -472,10 +493,17 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > int cfg = event->attr.config; > int cfg1 = event->attr.config1; > int cfg2 = event->attr.config2; > - int counter; > + int event_id, counter; > > + event_id = FIELD_GET(CONFIG_EVENT, cfg); > counter = FIELD_GET(CONFIG_COUNTER, cfg); > > + counter = ddr_perf_alloc_counter(pmu, event_id, counter); > + if (counter < 0) { > + dev_dbg(pmu->dev, "There are not enough counters\n"); > + return -EOPNOTSUPP; > + } > + > pmu->events[counter] = event; > pmu->active_events++; > hwc->idx = counter; > @@ -485,7 +513,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > ddr_perf_event_start(event, flags); > > /* read trans, write trans, read beat */ > - ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); > + ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > return 0; > } > @@ -506,9 +534,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags) > { > struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); > struct hw_perf_event *hwc = &event->hw; > + int counter = hwc->idx; > > ddr_perf_event_stop(event, PERF_EF_UPDATE); > > + pmu->events[counter] = NULL; > pmu->active_events--; > hwc->idx = -1; > } > -- > 2.34.1 >
On Fri, Mar 15, 2024 at 05:55:51PM +0800, Xu Yang wrote: > This driver is initinally used to support imx93 Soc and now it's time to > add support for imx95 Soc. However, some macro definitions and events are > different on these two Socs. For preparing imx95 supports, this will > refactor driver for imx93. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > --- > Changes in v4: > - new patch > Changes in v5: > - use is_visible to hide unwanted attributes as suggested by Will > Changes in v6: > - improve imx93_ddr_perf_monitor_config() > Changes in v7: > - improve imx93_ddr_perf_monitor_config() as suggested by Frank > --- > drivers/perf/fsl_imx9_ddr_perf.c | 80 +++++++++++++++++++------------- > 1 file changed, 47 insertions(+), 33 deletions(-) > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > index 4fdf8bcf6646..5537f4e07852 100644 > --- a/drivers/perf/fsl_imx9_ddr_perf.c > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > @@ -11,14 +11,14 @@ > #include <linux/perf_event.h> > > /* Performance monitor configuration */ > -#define PMCFG1 0x00 > -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) > -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) > -#define PMCFG1_RD_BT_FILT_EN BIT(29) > -#define PMCFG1_ID_MASK GENMASK(17, 0) > +#define PMCFG1 0x00 > +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) > +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) > +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) > +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) > > -#define PMCFG2 0x04 > -#define PMCFG2_ID GENMASK(17, 0) > +#define PMCFG2 0x04 > +#define MX93_PMCFG2_ID GENMASK(17, 0) > > /* Global control register affects all counters and takes priority over local control registers */ > #define PMGC0 0x40 > @@ -76,6 +76,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { > .identifier = "imx93", > }; > > +static inline bool is_imx93(struct ddr_pmu *pmu) > +{ > + return pmu->devtype_data == &imx93_devtype_data; > +} > + > static const struct of_device_id imx_ddr_pmu_dt_ids[] = { > {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, > { /* sentinel */ } > @@ -185,7 +190,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ > > /* counter3 specific events */ > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), > @@ -197,7 +202,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ > > /* counter4 specific events */ > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), > @@ -209,7 +214,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ > > /* counter5 specific events */ > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), > @@ -244,9 +249,26 @@ static struct attribute *ddr_perf_events_attrs[] = { > NULL, > }; > > +static umode_t > +ddr_perf_events_attrs_is_visible(struct kobject *kobj, > + struct attribute *attr, int unused) > +{ > + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); > + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > + > + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") || > + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") || > + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) && > + !is_imx93(ddr_pmu)) > + return 0; I think use name to check visible is not good enough. struct imx9_pmu_events_attr { struct perf_pmu_events_attr perf_attr; void * drv_data; }; #define IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, drv_data) \ (&((struct imx9_pmu_events_attr[]) { \ { .perf_attr.attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ .perf_attr.id = _id, .drv_data = drv_data, } \ })[0].perf_attr.attr.attr) #define IMX9_DDR_PMU_EVENT_ATTR(_namee, _id,) IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, NULL) #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, &imx93_devtype_data) So ddr_perf_events_attrs_is_visible() { struct imx9_pmu_events_attr *imx9_attr = container_of(attr, imx9_pmu_events_attr, perf_attr) if (!imx9_attr->drv_data) return attr->mode; if (imx9_attr->drv_data ! = ddr_pmu->drv_data) return 0; return attr->mode; } Frank > + > + return attr->mode; > +} > + > static const struct attribute_group ddr_perf_events_attr_group = { > .name = "events", > .attrs = ddr_perf_events_attrs, > + .is_visible = ddr_perf_events_attrs_is_visible, > }; > > PMU_FORMAT_ATTR(event, "config:0-15"); > @@ -368,36 +390,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, > } > } > > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, > - int counter, int axi_id, int axi_mask) > +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, > + int counter, int axi_id, int axi_mask) > { > u32 pmcfg1, pmcfg2; > + u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN, > + MX93_PMCFG1_WR_TRANS_FILT_EN, > + MX93_PMCFG1_RD_BT_FILT_EN }; > > pmcfg1 = readl_relaxed(pmu->base + PMCFG1); > > - if (counter == 2 && event == 73) > - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; > - else if (counter == 2 && event != 73) > - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; > - > - if (counter == 3 && event == 73) > - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; > - else if (counter == 3 && event != 73) > - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; > - > - if (counter == 4 && event == 73) > - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; > - else if (counter == 4 && event != 73) > - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; > + if (counter >= 2 && counter <= 4) > + pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] : > + pmcfg1 & ~mask[counter - 2]; > > - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); > - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); > - writel(pmcfg1, pmu->base + PMCFG1); > + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); > + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask); > + writel_relaxed(pmcfg1, pmu->base + PMCFG1); > > pmcfg2 = readl_relaxed(pmu->base + PMCFG2); > - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); > - pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id); > - writel(pmcfg2, pmu->base + PMCFG2); > + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); > + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id); > + writel_relaxed(pmcfg2, pmu->base + PMCFG2); > } > > static void ddr_perf_event_update(struct perf_event *event) > @@ -513,7 +527,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > ddr_perf_event_start(event, flags); > > /* read trans, write trans, read beat */ > - ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > return 0; > } > -- > 2.34.1 >
On Fri, Mar 15, 2024 at 05:55:52PM +0800, Xu Yang wrote: > In current driver, the counter will start firstly and then be configured. > This sequence is not correct for AXI filter events since the correct > AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> This one should be bug fix. Can you add fixes tag? > > --- > Changes in v5: > - new patch > Changes in v6: > - no changes > Changes in v7: > - no changes > --- > drivers/perf/fsl_imx9_ddr_perf.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > index 5537f4e07852..c99c43b214cb 100644 > --- a/drivers/perf/fsl_imx9_ddr_perf.c > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > @@ -523,12 +523,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > hwc->idx = counter; > hwc->state |= PERF_HES_STOPPED; > > - if (flags & PERF_EF_START) > - ddr_perf_event_start(event, flags); > - > /* read trans, write trans, read beat */ > imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > + if (flags & PERF_EF_START) > + ddr_perf_event_start(event, flags); > + > return 0; > } > > -- > 2.34.1 >
On Mon, Mar 18, 2024 at 06:18:52AM +0000, Xu Yang wrote: > Hi Arnaldo, > > > > > On Fri, Mar 15, 2024 at 05:55:54PM +0800, Xu Yang wrote: > > > Add JSON metrics for i.MX95 DDR Performance Monitor. > > > > > > Reviewed-by: John Garry <john.g.garry@oracle.com> > > > Reviewed-by: Ian Rogers <irogers@google.com> > > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > > > I'm applying the tools/perf/ patches, that is 7/8 and 8/8, but I noticed > > that 8/8 has no Reviewed-by tags, is that really the case? If so, can we > > have them? > > I found IMX93 metrics are still not added until v6, then I add patch 8/8 in v7. > So it's still waiting for review I think. Sorry for inconvenience. Ok, so lets wait a bit more for review. - Arnaldo > Thanks, > Xu Yang > > > > > - Arnaldo > > > > > --- > > > Changes in v2: > > > - fix wrong AXI_MASK setting > > > - remove unnecessary metrics > > > - add bandwidth_usage, camera_all, disp_all metrics > > > Changes in v3: > > > - no changes > > > Changes in v4: > > > - add Reviewed-by tag > > > Changes in v5: > > > - fix typo > > > Changes in v6: > > > - remove "counter=X" from each metric > > > Changes in v7: > > > - add RB tag > > > --- > > > .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + > > > .../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++ > > > tools/perf/pmu-events/jevents.py | 1 + > > > 3 files changed, 788 insertions(+) > > > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > > > create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > > > > > > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu- > > events/arch/arm64/freescale/imx95/sys/ddrc.json > > > new file mode 100644 > > > index 000000000000..4dc9d2968bdc > > > --- /dev/null > > > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json > > > @@ -0,0 +1,9 @@ > > > +[ > > > + { > > > + "BriefDescription": "ddr cycles event", > > > + "EventCode": "0x00", > > > + "EventName": "imx95_ddr.cycles", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + } > > > +] > > > diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu- > > events/arch/arm64/freescale/imx95/sys/metrics.json > > > new file mode 100644 > > > index 000000000000..a3ae787d448c > > > --- /dev/null > > > +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json > > > @@ -0,0 +1,778 @@ > > > +[ > > > + { > > > + "BriefDescription": "bandwidth usage for lpddr5 evk board", > > > + "MetricName": "imx95_bandwidth_usage.lpddr5", > > > + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + > > imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * > > 4)", > > > + "ScaleUnit": "1e2%", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all masters read from ddr", > > > + "MetricName": "imx95_ddr_read.all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all masters write to ddr", > > > + "MetricName": "imx95_ddr_write.all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all a55 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + > > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all a55 write to ddr (part1)", > > > + "MetricName": "imx95_ddr_write.a55_all_1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all a55 write to ddr (part2)", > > > + "MetricName": "imx95_ddr_write.a55_all_2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 0 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_0", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 0 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_0", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 1 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 1 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 2 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 2 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 3 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 3 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 4 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_4", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 4 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_4", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 5 read from ddr", > > > + "MetricName": "imx95_ddr_read.a55_5", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of a55 core 5 write to ddr", > > > + "MetricName": "imx95_ddr_write.a55_5", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", > > > + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", > > > + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x007@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of m33 read from ddr", > > > + "MetricName": "imx95_ddr_read.m33", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of m33 write to ddr", > > > + "MetricName": "imx95_ddr_write.m33", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of m7 read from ddr", > > > + "MetricName": "imx95_ddr_read.m7", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of m7 write to ddr", > > > + "MetricName": "imx95_ddr_write.m7", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of sentinel read from ddr", > > > + "MetricName": "imx95_ddr_read.sentinel", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of sentinel write to ddr", > > > + "MetricName": "imx95_ddr_write.sentinel", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of edma1 read from ddr", > > > + "MetricName": "imx95_ddr_read.edma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of edma1 write to ddr", > > > + "MetricName": "imx95_ddr_write.edma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of edma2 read from ddr", > > > + "MetricName": "imx95_ddr_read.edma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of edma2 write to ddr", > > > + "MetricName": "imx95_ddr_write.edma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of netc read from ddr", > > > + "MetricName": "imx95_ddr_read.netc", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of netc write to ddr", > > > + "MetricName": "imx95_ddr_write.netc", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of npu read from ddr", > > > + "MetricName": "imx95_ddr_read.npu", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of npu write to ddr", > > > + "MetricName": "imx95_ddr_write.npu", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x010@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of gpu read from ddr", > > > + "MetricName": "imx95_ddr_read.gpu", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of gpu write to ddr", > > > + "MetricName": "imx95_ddr_write.gpu", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc1 read from ddr", > > > + "MetricName": "imx95_ddr_read.usdhc1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc1 write to ddr", > > > + "MetricName": "imx95_ddr_write.usdhc1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc2 read from ddr", > > > + "MetricName": "imx95_ddr_read.usdhc2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc2 write to ddr", > > > + "MetricName": "imx95_ddr_write.usdhc2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0c0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc3 read from ddr", > > > + "MetricName": "imx95_ddr_read.usdhc3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usdhc3 write to ddr", > > > + "MetricName": "imx95_ddr_write.usdhc3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of xspi read from ddr", > > > + "MetricName": "imx95_ddr_read.xspi", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of xspi write to ddr", > > > + "MetricName": "imx95_ddr_write.xspi", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie1 read from ddr", > > > + "MetricName": "imx95_ddr_read.pcie1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie1 write to ddr", > > > + "MetricName": "imx95_ddr_write.pcie1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie2 read from ddr", > > > + "MetricName": "imx95_ddr_read.pcie2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie2 write to ddr", > > > + "MetricName": "imx95_ddr_write.pcie2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie3 read from ddr", > > > + "MetricName": "imx95_ddr_read.pcie3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie3 write to ddr", > > > + "MetricName": "imx95_ddr_write.pcie3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x120@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie4 read from ddr", > > > + "MetricName": "imx95_ddr_read.pcie4", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of pcie4 write to ddr", > > > + "MetricName": "imx95_ddr_write.pcie4", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x130@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usb1 read from ddr", > > > + "MetricName": "imx95_ddr_read.usb1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usb1 write to ddr", > > > + "MetricName": "imx95_ddr_write.usb1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x140@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usb2 read from ddr", > > > + "MetricName": "imx95_ddr_read.usb2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of usb2 write to ddr", > > > + "MetricName": "imx95_ddr_write.usb2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x150@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of vpu codec primary bus read from ddr", > > > + "MetricName": "imx95_ddr_read.vpu_primy", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of vpu codec primary bus write to ddr", > > > + "MetricName": "imx95_ddr_write.vpu_primy", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x180@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", > > > + "MetricName": "imx95_ddr_read.vpu_secndy", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", > > > + "MetricName": "imx95_ddr_write.vpu_secndy", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of jpeg decoder read from ddr", > > > + "MetricName": "imx95_ddr_read.jpeg_dec", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of jpeg decoder write to ddr", > > > + "MetricName": "imx95_ddr_write.jpeg_dec", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of jpeg encoder read from ddr", > > > + "MetricName": "imx95_ddr_read.jpeg_dec", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of jpeg encoder write to ddr", > > > + "MetricName": "imx95_ddr_write.jpeg_enc", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all vpu submodules read from ddr", > > > + "MetricName": "imx95_ddr_read.vpu_all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all vpu submodules write to ddr", > > > + "MetricName": "imx95_ddr_write.vpu_all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of cortex m0+ read from ddr", > > > + "MetricName": "imx95_ddr_read.m0", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of cortex m0+ write to ddr", > > > + "MetricName": "imx95_ddr_write.m0", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of camera edma read from ddr", > > > + "MetricName": "imx95_ddr_read.camera_edma", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of camera edma write to ddr", > > > + "MetricName": "imx95_ddr_write.camera_edma", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi rd read from ddr", > > > + "MetricName": "imx95_ddr_read.isi_rd", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi rd write to ddr", > > > + "MetricName": "imx95_ddr_write.isi_rd", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr y read from ddr", > > > + "MetricName": "imx95_ddr_read.isi_wr_y", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr y write to ddr", > > > + "MetricName": "imx95_ddr_write.isi_wr_y", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr u read from ddr", > > > + "MetricName": "imx95_ddr_read.isi_wr_u", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr u write to ddr", > > > + "MetricName": "imx95_ddr_write.isi_wr_u", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr v read from ddr", > > > + "MetricName": "imx95_ddr_read.isi_wr_v", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isi wr v write to ddr", > > > + "MetricName": "imx95_ddr_write.isi_wr_v", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp input dma1 read from ddr", > > > + "MetricName": "imx95_ddr_read.isp_in_dma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp input dma1 write to ddr", > > > + "MetricName": "imx95_ddr_write.isp_in_dma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp input dma2 read from ddr", > > > + "MetricName": "imx95_ddr_read.isp_in_dma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp input dma2 write to ddr", > > > + "MetricName": "imx95_ddr_write.isp_in_dma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp output dma1 read from ddr", > > > + "MetricName": "imx95_ddr_read.isp_out_dma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp output dma1 write to ddr", > > > + "MetricName": "imx95_ddr_write.isp_out_dma1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp output dma2 read from ddr", > > > + "MetricName": "imx95_ddr_read.isp_out_dma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of isp output dma2 write to ddr", > > > + "MetricName": "imx95_ddr_write.isp_out_dma2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all camera submodules read from ddr", > > > + "MetricName": "imx95_ddr_read.camera_all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + > > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + > > imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", > > > + "MetricName": "imx95_ddr_write.camera_all_1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", > > > + "MetricName": "imx95_ddr_write.camera_all_2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", > > > + "MetricName": "imx95_ddr_write.camera_all_3", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of display blitter store read from ddr", > > > + "MetricName": "imx95_ddr_read.disp_blit", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of display blitter write to ddr", > > > + "MetricName": "imx95_ddr_write.disp_blit", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of display command sequencer read from ddr", > > > + "MetricName": "imx95_ddr_read.disp_cmd", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of display command sequencer write to ddr", > > > + "MetricName": "imx95_ddr_write.disp_cmd", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all display submodules read from ddr", > > > + "MetricName": "imx95_ddr_read.disp_all", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + > > imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all display submodules write to ddr (part1)", > > > + "MetricName": "imx95_ddr_write.disp_all_1", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + }, > > > + { > > > + "BriefDescription": "bytes of all display submodules write to ddr (part2)", > > > + "MetricName": "imx95_ddr_write.disp_all_2", > > > + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", > > > + "ScaleUnit": "9.765625e-4KB", > > > + "Unit": "imx9_ddr", > > > + "Compat": "imx95" > > > + } > > > +] > > > diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py > > > index 53ab050c8fa4..be4b541a0820 100755 > > > --- a/tools/perf/pmu-events/jevents.py > > > +++ b/tools/perf/pmu-events/jevents.py > > > @@ -284,6 +284,7 @@ class JsonEvent: > > > 'hisi_sccl,hha': 'hisi_sccl,hha', > > > 'hisi_sccl,l3c': 'hisi_sccl,l3c', > > > 'imx8_ddr': 'imx8_ddr', > > > + 'imx9_ddr': 'imx9_ddr', > > > 'L3PMC': 'amd_l3', > > > 'DFPMC': 'amd_df', > > > 'UMCPMC': 'amd_umc', > > > -- > > > 2.34.1
> > On Fri, Mar 15, 2024 at 05:55:51PM +0800, Xu Yang wrote: > > This driver is initinally used to support imx93 Soc and now it's time to > > add support for imx95 Soc. However, some macro definitions and events are > > different on these two Socs. For preparing imx95 supports, this will > > refactor driver for imx93. > > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > > > --- > > Changes in v4: > > - new patch > > Changes in v5: > > - use is_visible to hide unwanted attributes as suggested by Will > > Changes in v6: > > - improve imx93_ddr_perf_monitor_config() > > Changes in v7: > > - improve imx93_ddr_perf_monitor_config() as suggested by Frank > > --- > > drivers/perf/fsl_imx9_ddr_perf.c | 80 +++++++++++++++++++------------- > > 1 file changed, 47 insertions(+), 33 deletions(-) > > > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > > index 4fdf8bcf6646..5537f4e07852 100644 > > --- a/drivers/perf/fsl_imx9_ddr_perf.c > > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > > @@ -11,14 +11,14 @@ > > #include <linux/perf_event.h> > > > > /* Performance monitor configuration */ > > -#define PMCFG1 0x00 > > -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) > > -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) > > -#define PMCFG1_RD_BT_FILT_EN BIT(29) > > -#define PMCFG1_ID_MASK GENMASK(17, 0) > > +#define PMCFG1 0x00 > > +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) > > +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) > > +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) > > +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) > > > > -#define PMCFG2 0x04 > > -#define PMCFG2_ID GENMASK(17, 0) > > +#define PMCFG2 0x04 > > +#define MX93_PMCFG2_ID GENMASK(17, 0) > > > > /* Global control register affects all counters and takes priority over local control registers */ > > #define PMGC0 0x40 > > @@ -76,6 +76,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { > > .identifier = "imx93", > > }; > > > > +static inline bool is_imx93(struct ddr_pmu *pmu) > > +{ > > + return pmu->devtype_data == &imx93_devtype_data; > > +} > > + > > static const struct of_device_id imx_ddr_pmu_dt_ids[] = { > > {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, > > { /* sentinel */ } > > @@ -185,7 +190,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), > > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), > > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), > > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ > > > > /* counter3 specific events */ > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), > > @@ -197,7 +202,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), > > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), > > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), > > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ > > > > /* counter4 specific events */ > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), > > @@ -209,7 +214,7 @@ static struct attribute *ddr_perf_events_attrs[] = { > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), > > IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), > > - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), > > + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ > > > > /* counter5 specific events */ > > IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), > > @@ -244,9 +249,26 @@ static struct attribute *ddr_perf_events_attrs[] = { > > NULL, > > }; > > > > +static umode_t > > +ddr_perf_events_attrs_is_visible(struct kobject *kobj, > > + struct attribute *attr, int unused) > > +{ > > + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); > > + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > > + > > + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") || > > + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") || > > + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) && > > + !is_imx93(ddr_pmu)) > > + return 0; > > I think use name to check visible is not good enough. Yeah, I failed to find out a better way to deal with it. > > struct imx9_pmu_events_attr > { > struct perf_pmu_events_attr perf_attr; > void * drv_data; > }; > > #define IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, drv_data) \ > (&((struct imx9_pmu_events_attr[]) { \ > { .perf_attr.attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ > .perf_attr.id = _id, > .drv_data = drv_data, > } \ > })[0].perf_attr.attr.attr) > > #define IMX9_DDR_PMU_EVENT_ATTR(_namee, _id,) > IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, NULL) > > #define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) > IMX9_DDR_PMU_EVENT_ATTR_COM(_name, _id, &imx93_devtype_data) > > So > > ddr_perf_events_attrs_is_visible() > { > struct imx9_pmu_events_attr *imx9_attr = container_of(attr, imx9_pmu_events_attr, perf_attr) > > if (!imx9_attr->drv_data) > return attr->mode; > > if (imx9_attr->drv_data ! = ddr_pmu->drv_data) > return 0; > > return attr->mode; > } I've tried your suggestion, it works and make sense for me. I'll integrate this in next version. Thanks, Xu Yang > > Frank > > > + > > + return attr->mode; > > +} > > + > > static const struct attribute_group ddr_perf_events_attr_group = { > > .name = "events", > > .attrs = ddr_perf_events_attrs, > > + .is_visible = ddr_perf_events_attrs_is_visible, > > }; > > > > PMU_FORMAT_ATTR(event, "config:0-15"); > > @@ -368,36 +390,28 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, > > } > > } > > > > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, > > - int counter, int axi_id, int axi_mask) > > +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, > > + int counter, int axi_id, int axi_mask) > > { > > u32 pmcfg1, pmcfg2; > > + u32 mask[] = { MX93_PMCFG1_RD_TRANS_FILT_EN, > > + MX93_PMCFG1_WR_TRANS_FILT_EN, > > + MX93_PMCFG1_RD_BT_FILT_EN }; > > > > pmcfg1 = readl_relaxed(pmu->base + PMCFG1); > > > > - if (counter == 2 && event == 73) > > - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; > > - else if (counter == 2 && event != 73) > > - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; > > - > > - if (counter == 3 && event == 73) > > - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; > > - else if (counter == 3 && event != 73) > > - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; > > - > > - if (counter == 4 && event == 73) > > - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; > > - else if (counter == 4 && event != 73) > > - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; > > + if (counter >= 2 && counter <= 4) > > + pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] : > > + pmcfg1 & ~mask[counter - 2]; > > > > - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); > > - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, axi_mask); > > - writel(pmcfg1, pmu->base + PMCFG1); > > + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); > > + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask); > > + writel_relaxed(pmcfg1, pmu->base + PMCFG1); > > > > pmcfg2 = readl_relaxed(pmu->base + PMCFG2); > > - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); > > - pmcfg2 |= FIELD_PREP(PMCFG2_ID, axi_id); > > - writel(pmcfg2, pmu->base + PMCFG2); > > + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); > > + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id); > > + writel_relaxed(pmcfg2, pmu->base + PMCFG2); > > } > > > > static void ddr_perf_event_update(struct perf_event *event) > > @@ -513,7 +527,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > > ddr_perf_event_start(event, flags); > > > > /* read trans, write trans, read beat */ > > - ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > + imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > > > return 0; > > } > > -- > > 2.34.1 > >
> > On Fri, Mar 15, 2024 at 05:55:52PM +0800, Xu Yang wrote: > > In current driver, the counter will start firstly and then be configured. > > This sequence is not correct for AXI filter events since the correct > > AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate. > > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > This one should be bug fix. Can you add fixes tag? Sure. Thanks, Xu Yang > > > > > --- > > Changes in v5: > > - new patch > > Changes in v6: > > - no changes > > Changes in v7: > > - no changes > > --- > > drivers/perf/fsl_imx9_ddr_perf.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c > > index 5537f4e07852..c99c43b214cb 100644 > > --- a/drivers/perf/fsl_imx9_ddr_perf.c > > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > > @@ -523,12 +523,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) > > hwc->idx = counter; > > hwc->state |= PERF_HES_STOPPED; > > > > - if (flags & PERF_EF_START) > > - ddr_perf_event_start(event, flags); > > - > > /* read trans, write trans, read beat */ > > imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); > > > > + if (flags & PERF_EF_START) > > + ddr_perf_event_start(event, flags); > > + > > return 0; > > } > > > > -- > > 2.34.1 > >
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 6c96a4204e5d..37e8b98f2cdc 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -30,6 +30,9 @@ properties: - items: - const: fsl,imx8dxl-ddr-pmu - const: fsl,imx8-ddr-pmu + - items: + - const: fsl,imx95-ddr-pmu + - const: fsl,imx93-ddr-pmu reg: maxItems: 1