| Message ID | 20231221162051.2131202-2-sjakhade@cadence.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 21/12/2023 17:20, Swapnil Jakhade wrote: > Add a new optional input reference clock (pll1_refclk) for PLL1. > Update bindings to support dual reference clock multilink configurations. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 21/12/2023 18:20, Swapnil Jakhade wrote: > Add a new optional input reference clock (pll1_refclk) for PLL1. > Update bindings to support dual reference clock multilink configurations. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index dfb31314face..3893800f81b4 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -35,14 +35,18 @@ properties: minItems: 1 maxItems: 2 description: - PHY reference clock for 1 item. Must contain an entry in clock-names. - Optional Parent to enable output reference clock. + PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1). + pll1_refclk is optional and used for multi-protocol configurations requiring + separate reference clock for each protocol. + Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used. + Optional parent clock (phy_en_refclk) to enable a reference clock output feature + on some platforms to output either derived or received reference clock. clock-names: minItems: 1 items: - const: refclk - - const: phy_en_refclk + - enum: [ pll1_refclk, phy_en_refclk ] reg: minItems: 1
Add a new optional input reference clock (pll1_refclk) for PLL1. Update bindings to support dual reference clock multilink configurations. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> --- .../devicetree/bindings/phy/phy-cadence-torrent.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)