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Thu, 09 Nov 2023 11:14:05 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id pj9-20020a17090b4f4900b00282ecb631a9sm124069pjb.25.2023.11.09.11.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 11:14:04 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 1/3] dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" Date: Thu, 9 Nov 2023 14:13:52 -0500 Message-Id: <20231109191355.27738-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231109191355.27738-1-james.quinlan@broadcom.com> References: <20231109191355.27738-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver to deliberately place the RC HW one of three CLKREQ# modes. The "brcm,clkreq-mode" property allows the user to override the default setting. If this property is omitted, the default mode shall be "default". Signed-off-by: Jim Quinlan --- .../bindings/pci/brcm,stb-pcie.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..992b35e915a5 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,27 @@ properties: aspm-no-l0s: true + brcm,clkreq-mode: + description: A string that determines the operating + clkreq mode of the PCIe RC HW WRT controlling the refclk signal. + There are three different modes -- + "safe", which drives the + refclk signal unconditionally and will work for all devices but does + not provide any power savings; + "no-l1ss" -- which provides Clock Power Management, L0s, and + L1, but cannot provide L1 substate (L1SS) power + savings. If the downstream device connected to the RC is + L1SS capable AND the OS enables L1SS, all PCIe traffic + may abruptly halt, potentially hanging the system; + "default" -- which provides L0s, L1, and L1SS, but not + compliant to provide Clock Power Management; + specifically, may not be able to meet the Tclron max + timing of 400ns as specified in "Dynamic Clock Control", + section 3.2.5.2.2 of the PCIe spec. This situation is + atypical and should happen only with older devices. + $ref: /schemas/types.yaml#/definitions/string + enum: [ safe, no-l1ss, default ] + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to