| Message ID | 20230724150002.5645-5-sjakhade@cadence.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | PHY: Add support for dual refclk configurations in Cadence Torrent PHY driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Jul 24, 2023 at 05:00:01PM +0200, Swapnil Jakhade wrote: > TI J7200 uses Torrent SD0805 version which is a special version > derived from SD0801 that has an additional input reference clock. > Add a separate compatible for TI J7200 platforms. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> > --- > Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > index ddb86ee0cebf..e3a1efd61033 100644 > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml > @@ -20,6 +20,7 @@ properties: > compatible: > enum: > - cdns,torrent-phy > + - ti,j7200-serdes-10g > - ti,j721e-serdes-10g Should the number of clocks not be restricted dynamically based on the compatible, since only the 7200 requires the extra refclk?
On 24/07/2023 20:56, Conor Dooley wrote: > On Mon, Jul 24, 2023 at 05:00:01PM +0200, Swapnil Jakhade wrote: >> TI J7200 uses Torrent SD0805 version which is a special version >> derived from SD0801 that has an additional input reference clock. >> Add a separate compatible for TI J7200 platforms. >> >> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> >> --- >> Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml >> index ddb86ee0cebf..e3a1efd61033 100644 >> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml >> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml >> @@ -20,6 +20,7 @@ properties: >> compatible: >> enum: >> - cdns,torrent-phy >> + - ti,j7200-serdes-10g >> - ti,j721e-serdes-10g > > Should the number of clocks not be restricted dynamically based on the > compatible, since only the 7200 requires the extra refclk? > Yes, this is a good idea.
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index ddb86ee0cebf..e3a1efd61033 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -20,6 +20,7 @@ properties: compatible: enum: - cdns,torrent-phy + - ti,j7200-serdes-10g - ti,j721e-serdes-10g '#address-cells':
TI J7200 uses Torrent SD0805 version which is a special version derived from SD0801 that has an additional input reference clock. Add a separate compatible for TI J7200 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> --- Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 1 + 1 file changed, 1 insertion(+)