Message ID | 20230704091948.85247-2-william.qiu@starfivetech.com |
---|---|
State | Superseded, archived |
Headers | show |
Series | Add SPI module for StarFive JH7110 SoC | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success | |
robh/patch-applied | success | |
robh/dtbs-check | warning | build log |
robh/dt-meta-schema | success |
diff --git a/Documentation/devicetree/bindings/spi/spi-pl022.yaml b/Documentation/devicetree/bindings/spi/spi-pl022.yaml index 91e540a92faf..42bb34c39971 100644 --- a/Documentation/devicetree/bindings/spi/spi-pl022.yaml +++ b/Documentation/devicetree/bindings/spi/spi-pl022.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: spi-controller.yaml# + - $ref: /schemas/arm/primecell.yaml# # We need a select here so we don't match all nodes with 'arm,primecell' select: @@ -34,12 +35,16 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 2 clock-names: - items: - - const: sspclk - - const: apb_pclk + oneOf: + - items: + - const: apb_pclk + - items: + - const: sspclk + - const: apb_pclk pl022,autosuspend-delay: description: delay in ms following transfer completion before the
The SPI controller only need apb_pclk clock to work properly on JH7110 SoC, so there add minItems whose value is equal to 1. Other platforms do not have this constraint. Signed-off-by: William Qiu <william.qiu@starfivetech.com> --- Documentation/devicetree/bindings/spi/spi-pl022.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)