| Message ID | 20230214-apple_m2_pmu-v1-1-9c9213ab9b63@jannau.net |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Apple M2 PMU support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Tue, 14 Feb 2023 11:38:01 +0100, Janne Grunau wrote: > The PMUs on the Apple M2 cores avalanche and blizzard CPU are compatible > with M1 ones. As on M1 we don't know exactly what the counters count so > use a distinct compatible for each micro-architecture. > Apple's PMU counter description omits a counter for M2 so there > is some variation on the interpretation of the counters. > > Signed-off-by: Janne Grunau <j@jannau.net> > --- > Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index dbb6f3dc5ae5..e14358bf0b9c 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,avalanche-pmu + - apple,blizzard-pmu - apple,firestorm-pmu - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models
The PMUs on the Apple M2 cores avalanche and blizzard CPU are compatible with M1 ones. As on M1 we don't know exactly what the counters count so use a distinct compatible for each micro-architecture. Apple's PMU counter description omits a counter for M2 so there is some variation on the interpretation of the counters. Signed-off-by: Janne Grunau <j@jannau.net> --- Documentation/devicetree/bindings/arm/pmu.yaml | 2 ++ 1 file changed, 2 insertions(+)