| Message ID | 20220826120559.2122-2-shubhrajyoti.datta@amd.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | serial: pl011: Add xilinx uart | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On 26/08/2022 15:05, Shubhrajyoti Datta wrote: > Some of the implementations support only 32-bit accesses. > Add a parameter reg-io-width for such platforms. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index d8aed84abcd3..80af72859876 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -94,6 +94,12 @@ properties: resets: maxItems: 1 + reg-io-width: + description: + The size (in bytes) of the IO accesses that should be performed + on the device. + enum: [1, 4] + required: - compatible - reg
Some of the implementations support only 32-bit accesses. Add a parameter reg-io-width for such platforms. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> --- v4 Fix the bindings Documentation/devicetree/bindings/serial/pl011.yaml | 6 ++++++ 1 file changed, 6 insertions(+)