From patchwork Thu Aug 25 09:14:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 1670148 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=IK8t1Vwx; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4MCy3j6yXdz1yhC for ; Thu, 25 Aug 2022 19:15:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238574AbiHYJPK (ORCPT ); Thu, 25 Aug 2022 05:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229657AbiHYJPJ (ORCPT ); Thu, 25 Aug 2022 05:15:09 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17E3312D03; Thu, 25 Aug 2022 02:14:59 -0700 (PDT) X-UUID: 38e818b9c7a84807a68c81bd719794c7-20220825 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=d27K2ZYpgSlJivuuUIEZmgJTuKQyXeb2NK4ggG+e144=; b=IK8t1VwxfVc6qKsG2+psKpSLeKecmgwjjMSyIP8CdFQ35lXCsTTehjgfnknEmzsUR3Ea5gn5DSj7IRowHD0rOvW/dDRJREQpcNzIswt0b7417iyBUQ+kdif67ueuc2FC2I85bf8JCXJJDlUAHk/ILpjA8DjVpw76FWGnC2a0p1w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.10,REQID:c8b035c6-4ca2-43ad-943f-741063b39028,OB:0,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_ Ham,ACTION:release,TS:0 X-CID-META: VersionHash:84eae18,CLOUDID:e9098c55-e800-47dc-8adf-0c936acf4f1b,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 38e818b9c7a84807a68c81bd719794c7-20220825 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 822603366; Thu, 25 Aug 2022 17:14:51 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 25 Aug 2022 17:14:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 25 Aug 2022 17:14:49 +0800 From: Bo-Chen Chen To: , , CC: , , , , , , , , , , , Bo-Chen Chen Subject: [PATCH v2] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Date: Thu, 25 Aug 2022 17:14:48 +0800 Message-ID: <20220825091448.14008-1-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,URIBL_BLOCKED,URIBL_CSS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: "Jason-JH.Lin" For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same clock driver and the same mediatek-drm driver. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1. Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0. To summarize0: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment. Therefore, we need to separate these two different mmsys hardwares to 2 different compatibles for MT8195. Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding") Signed-off-by: Jason-JH.Lin Signed-off-by: Bo-Chen Chen Acked-by: Krzysztof Kozlowski --- Changes for v2: 1. Add hardware difference for VDOSYS0 and VDOSYS1 in commit message. --- .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 6ad023eec193..bfbdd30d2092 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -31,7 +31,8 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys - - mediatek,mt8195-mmsys + - mediatek,mt8195-vdosys0 + - mediatek,mt8195-vdosys1 - mediatek,mt8365-mmsys - const: syscon - items: