| Message ID | 20220502125015.1345312-2-niklas.cassel@wdc.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v2,1/2] dt-bindings: riscv: Add mmu-type riscv,sv57 | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 1 warnings, 7 lines checked |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, May 2, 2022 at 6:20 PM Niklas Cassel <niklas.cassel@wdc.com> wrote: > > sv57 is defined in the RISC-V Privileged Specification document. > > Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly") > changed the default MMU mode to sv57, if supported by current hardware. > > Add riscv,sv57 to the list of valid mmu-type values. > > Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> > Acked-by: Rob Herring <robh@kernel.org> Looks good to me. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d632ac76532e..3100fa233ca4 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -61,6 +61,7 @@ properties: > - riscv,sv32 > - riscv,sv39 > - riscv,sv48 > + - riscv,sv57 > - riscv,none > > riscv,isa: > -- > 2.35.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..3100fa233ca4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,sv57 - riscv,none riscv,isa:
sv57 is defined in the RISC-V Privileged Specification document. Additionally, commit 011f09d12052 ("riscv: mm: Set sv57 on defaultly") changed the default MMU mode to sv57, if supported by current hardware. Add riscv,sv57 to the list of valid mmu-type values. Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com> Acked-by: Rob Herring <robh@kernel.org> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)