From patchwork Thu Feb 10 07:45:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 1590876 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=GSn2Irip; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by bilbo.ozlabs.org (Postfix) with ESMTP id 4JvTP366x5z9s9c for ; Thu, 10 Feb 2022 18:47:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236535AbiBJHrc (ORCPT ); Thu, 10 Feb 2022 02:47:32 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:56980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236515AbiBJHrb (ORCPT ); Thu, 10 Feb 2022 02:47:31 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9E2BD72; Wed, 9 Feb 2022 23:47:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644479252; x=1676015252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=p5j3Riq4rZoEYGYuDL+O+9dYmiRcXLURQv7yhYMS5TU=; b=GSn2Iripkeeel30kuDZaRfSXqlJV5BCTDuu6aFuiG91lpbMtN62Qfqe2 7y4Puz0kouFXp6SdV7pcxju4iFROoWl7hRbiqe3+AZggBf+OPCi1kiWQY CP26I0+OvN70MilTvZm29W+r1xt+TgPYE6YZIE96eICBSrKuEWMgsnwUa rTWArnU0GgiXag/wxY3dAwQ6Yj8SbcRK/uEgHVG9Ig64XIKwgWWcUO1be qieJIeQukzCD25KNv7ikUX5UkwzcNQk4AZl3OacZJzX3Ah/kKAXqvg9WS pMs0Eegz8Q4It4r2NiOZadcz0veyT7LKKbgB2/cWyByT8eerfCeYC7X9w Q==; IronPort-SDR: fCkB7qWlsJB1wyrTVx4IvHtQx9f+M62Ua5A8rFGAoHUNZW8m4omgDm7Z9Ho3IuJjrCVDSslfb6 WC6UUL5YzxUIOmwLxTuIdj0rcZNbdpOvH+MoNMOKx6fb2FUU3TQAq7yxUDTOxqJtszhcXWrUcl 8ofBh8dzksaznTRTX8w/026LR+gxwSHoTc4hwUsxJMBGqyzyuSTUemgphqw+wk5iFWp7ODOg+Q ERv3DkZmv5aCmdu2Iogzf4nYwqAq983usvHEsy+JZdNEz1m1eiM/heHcZ+eQGsq1NdPSH9HiA7 YE0hREDR8y5H54bQ9TmqWCIE X-IronPort-AV: E=Sophos;i="5.88,358,1635231600"; d="scan'208";a="85274949" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Feb 2022 00:47:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 10 Feb 2022 00:47:31 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 10 Feb 2022 00:47:27 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , Subject: [PATCH 1/2] mfd: dt-bindings: add bindings for lan966 flexcom shared configurations Date: Thu, 10 Feb 2022 13:15:45 +0530 Message-ID: <20220210074546.30669-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> References: <20220210074546.30669-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds LAN966 SoC DT bindings documentation for Flexcom Shared and chip-select configurations. Signed-off-by: Kavyasree Kotagiri --- .../devicetree/bindings/mfd/atmel-flexcom.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt index 692300117c64..a76622082228 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt @@ -18,6 +18,15 @@ Required properties: - <2> for SPI - <3> for I2C +Optional properties: +- Flexcom shared configurations: Each flexcom of lan966 SoC has 2 chip selects. + For each chip select, there is a pin configuration register. + The width of the configuration register is 21 because there are 21 shared + pins on each of which the chip select can be mapped. Each bit of the + configuration register represents a different FLEXCOM_SHARED pin. + - lan966x-ss-pin: Should be a flexcom shared pin. + - lan966x-cs: Should be chip select 0 or 1. + Required child: A single available child device of type matching the "atmel,flexcom-mode" property. @@ -41,6 +50,9 @@ flexcom@f8034000 { #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; + /* Map chip-select index 0 of the flexcom to FLEXCOM_SHARED 9 */ + lan966x-ss-pin = <9>; + lan966x-cs = <0>; spi@400 { compatible = "atmel,at91rm9200-spi";