| Message ID | 20211022170236.18839-15-sjakhade@cadence.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show
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From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
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CC: <mparab@cadence.com>, <sjakhade@cadence.com>, <a-govindraju@ti.com>
Subject: [PATCH v3 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for
derived reference clock
Date: Fri, 22 Oct 2021 19:02:35 +0200
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|
| Series |
PHY: Add support for multilink configurations in Cadence Sierra PHY driver
|
expand
|
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h index d55fe6e6b936..0671991208fc 100644 --- a/include/dt-bindings/phy/phy-cadence.h +++ b/include/dt-bindings/phy/phy-cadence.h @@ -18,5 +18,6 @@ /* Sierra */ #define CDNS_SIERRA_PLL_CMNLC 0 #define CDNS_SIERRA_PLL_CMNLC1 1 +#define CDNS_SIERRA_DERIVED_REFCLK 2 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */