From patchwork Mon Sep 20 09:52:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Horatiu Vultur X-Patchwork-Id: 1530041 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=uAxNDDin; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4HCfwn2Qw8z9svs for ; Mon, 20 Sep 2021 19:52:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236924AbhITJxb (ORCPT ); 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d="scan'208";a="137192394" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Sep 2021 02:51:31 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Mon, 20 Sep 2021 02:51:31 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Mon, 20 Sep 2021 02:51:28 -0700 From: Horatiu Vultur To: , , , , , , , , , , , , , CC: Horatiu Vultur Subject: [RFC PATCH net-next 06/12] dt-bindings: reset: Add lan966x power reset bindings Date: Mon, 20 Sep 2021 11:52:12 +0200 Message-ID: <20210920095218.1108151-7-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210920095218.1108151-1-horatiu.vultur@microchip.com> References: <20210920095218.1108151-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the lan966x power reset device driver bindings Signed-off-by: Horatiu Vultur --- .../bindings/power/lan966x,power.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/lan966x,power.yaml diff --git a/Documentation/devicetree/bindings/power/lan966x,power.yaml b/Documentation/devicetree/bindings/power/lan966x,power.yaml new file mode 100644 index 000000000000..d10eec10089b --- /dev/null +++ b/Documentation/devicetree/bindings/power/lan966x,power.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/lan966x,power.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Lan966x Power Reset Controller + +maintainers: + - Horatiu Vultur + - UNGLinuxDriver@microchip.com + +description: | + The Microchip Lan966x SoC provides power reset control. + +properties: + $nodename: + pattern: "^chip-controller$" + + compatible: + const: microchip,lan966x-chip-reset + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + + switch-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access SWITCH reset + +required: + - compatible + - "#reset-cells" + - cpu-syscon + - switch-syscon + +additionalProperties: false + +examples: + - | + reset: chip-controller { + compatible = "microchip,lan966x-chip-reset"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + switch-syscon = <&switch_ctrl>; + };