From patchwork Fri Sep 10 06:06:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 1526374 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=0sl/isql; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H5QS94WCGz9sW5 for ; Fri, 10 Sep 2021 16:09:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbhIJGKX (ORCPT ); Fri, 10 Sep 2021 02:10:23 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:42651 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230417AbhIJGKW (ORCPT ); Fri, 10 Sep 2021 02:10:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1631254152; x=1662790152; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=79y9TXD3dcFgndpcLNjdDOfeh8j5FX06J40EZLTDGN0=; b=0sl/isql8xdRYgO6KqztC93EjTsCFbThdFPyEdK7uLm8rhF19UA7zC24 8u63/P2OIWdFJR+lwoKJjntIAj6YpE9G2CHKeChKo7d8ii0yhv0WlGHIJ nXaTodF4avl438atjYKdZufT9RJ8EJuDb4fWjsMaj6C8abZfCHY8QDtih lT8zRk+JW/1/15weTREulSLv2tTmF7GgVG/vMI00ZHgeOYnOVPdzgghLP NlHwIjbkHvCR42iR8BSgRNQg7cBNsM5BZdLjf8dBx6oFqe5mL3BP51RDb dpglibGygOnxH7AKFM5qKlvUz3Yt/njiV5MtUwShlQX/YiOaO/aOuOOOx g==; IronPort-SDR: NLRIAwBnJaxNjQ5MzNE6QYfygnbpkuz/2Ak6gB4x9xKsK1H5EsTJ+wgTxNqHt/Ej+Zbts+OcnO x773hmut2G0hHrlcqNV4ZvHBbim7/gyN7NOTJ8iatDQijaTHkRUeqMJliat70DvMLVz/lgvOvZ 8pmMdEBUWWEnGRh8d9JFSF37c9KuT27U2xtWAjoRmr2Zj+Am6nZ3xhe0zxdbqEgCfKUtRVRxyi sObmOfxrGm4tN/bgsEFLouRqQYLMcN2Dg2YZzYDqvWf2eOZ3sq3kHe/Lqt/WEVD7vk3akoqiDm pF+00oLdaIV5NdhjM0l5wTfL X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="143607058" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Sep 2021 23:09:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 9 Sep 2021 23:09:11 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 9 Sep 2021 23:09:07 -0700 From: Claudiu Beznea To: , , CC: , , , Claudiu Beznea Subject: [PATCH v3 1/2] dt-bindings: microchip,eic: add bindings Date: Fri, 10 Sep 2021 09:06:55 +0300 Message-ID: <20210910060656.1061234-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210910060656.1061234-1-claudiu.beznea@microchip.com> References: <20210910060656.1061234-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings for Microchip External Interrupt Controller. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../interrupt-controller/microchip,eic.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml new file mode 100644 index 000000000000..50003880ee6f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip External Interrupt Controller + +maintainers: + - Claudiu Beznea + +description: + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides + support for handling up to 2 external interrupt lines. + +properties: + compatible: + enum: + - microchip,sama7g5-eic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the input IRQ number (between 0 and 1), the second cell + is the trigger type as defined in interrupt.txt present in this directory. + + interrupts: + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. They + should be specified sequentially from output 0 to output 1. + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0x100>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + }; + +...