| Message ID | 20210908122930.10224-15-sjakhade@cadence.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show
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From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
CC: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>,
<a-govindraju@ti.com>
Subject: [PATCH v2 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for
derived reference clock
Date: Wed, 8 Sep 2021 14:29:29 +0200
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|
| Series |
PHY: Add support for multilink configurations in Cadence Sierra PHY driver
|
expand
|
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Wed, 08 Sep 2021 14:29:29 +0200, Swapnil Jakhade wrote: > Add clock ID for Sierra derived reference clock. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> > --- > include/dt-bindings/phy/phy-cadence.h | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h index abc4ff81aa7b..a6c58fd46b35 100644 --- a/include/dt-bindings/phy/phy-cadence.h +++ b/include/dt-bindings/phy/phy-cadence.h @@ -16,5 +16,6 @@ /* Sierra */ #define CDNS_SIERRA_PLL_CMNLC 0 #define CDNS_SIERRA_PLL_CMNLC1 1 +#define CDNS_SIERRA_DERIVED_REFCLK 2 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */
Add clock ID for Sierra derived reference clock. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> --- include/dt-bindings/phy/phy-cadence.h | 1 + 1 file changed, 1 insertion(+)