| Message ID | 20210125235653.24385-2-s-anna@ti.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add HwSpinlock support for TI K3 AM64x SoCs | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success | |
| robh/dtbs-check | fail | build log |
On Mon, Jan 25, 2021 at 05:56:52PM -0600, Suman Anna wrote: > Update the existing OMAP HwSpinlock binding to include the info for > AM64x SoCs. There are some minor IP integration differences between > the AM64x SoCs and the previous AM65x and J721E SoC families. A new > example is also added showcasing the difference in the IP's presence > on the interconnect. > > Signed-off-by: Suman Anna <s-anna@ti.com> > --- > .../bindings/hwlock/ti,omap-hwspinlock.yaml | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > index ac35491a6f65..ac146c0d628f 100644 > --- a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > +++ b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > @@ -14,6 +14,7 @@ properties: > enum: > - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs > - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs > + - ti,am64-hwspinlock # for K3 AM64x SoCs > > reg: > maxItems: 1 > @@ -74,3 +75,28 @@ examples: > }; > }; > }; > + > + - | > + / { > + /* K3 AM64x SoCs */ > + model = "Texas Instruments K3 AM642 SoC"; > + compatible = "ti,am642-evm", "ti,am642"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + bus@f4000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ > + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ > + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ > + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>; /* Third peripheral window */ > + > + spinlock@2a000000 { Why are you doing the whole hierarchy here? Don't do that. In any case, a new compatible doesn't warrant a whole new example, so drop the example. > + compatible = "ti,am64-hwspinlock"; > + reg = <0x00 0x2a000000 0x00 0x1000>; > + #hwlock-cells = <1>; > + }; > + }; > + }; > -- > 2.29.2 >
Hi Rob, On 2/9/21 11:00 AM, Rob Herring wrote: > On Mon, Jan 25, 2021 at 05:56:52PM -0600, Suman Anna wrote: >> Update the existing OMAP HwSpinlock binding to include the info for >> AM64x SoCs. There are some minor IP integration differences between >> the AM64x SoCs and the previous AM65x and J721E SoC families. A new >> example is also added showcasing the difference in the IP's presence >> on the interconnect. >> >> Signed-off-by: Suman Anna <s-anna@ti.com> >> --- >> .../bindings/hwlock/ti,omap-hwspinlock.yaml | 26 +++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >> index ac35491a6f65..ac146c0d628f 100644 >> --- a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >> +++ b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >> @@ -14,6 +14,7 @@ properties: >> enum: >> - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs >> - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs >> + - ti,am64-hwspinlock # for K3 AM64x SoCs >> >> reg: >> maxItems: 1 >> @@ -74,3 +75,28 @@ examples: >> }; >> }; >> }; >> + >> + - | >> + / { >> + /* K3 AM64x SoCs */ >> + model = "Texas Instruments K3 AM642 SoC"; >> + compatible = "ti,am642-evm", "ti,am642"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + bus@f4000 { >> + compatible = "simple-bus"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ >> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ >> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ >> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>; /* Third peripheral window */ >> + >> + spinlock@2a000000 { > > Why are you doing the whole hierarchy here? Don't do that. I added it because it's integration is slightly different and to help our downstream consumers. > > In any case, a new compatible doesn't warrant a whole new example, so > drop the example. Yeah ok, will drop the example. regards Suman > >> + compatible = "ti,am64-hwspinlock"; >> + reg = <0x00 0x2a000000 0x00 0x1000>; >> + #hwlock-cells = <1>; >> + }; >> + }; >> + }; >> -- >> 2.29.2 >>
On Tue 09 Feb 11:09 CST 2021, Suman Anna wrote: > Hi Rob, > > On 2/9/21 11:00 AM, Rob Herring wrote: > > On Mon, Jan 25, 2021 at 05:56:52PM -0600, Suman Anna wrote: > >> Update the existing OMAP HwSpinlock binding to include the info for > >> AM64x SoCs. There are some minor IP integration differences between > >> the AM64x SoCs and the previous AM65x and J721E SoC families. A new > >> example is also added showcasing the difference in the IP's presence > >> on the interconnect. > >> > >> Signed-off-by: Suman Anna <s-anna@ti.com> > >> --- > >> .../bindings/hwlock/ti,omap-hwspinlock.yaml | 26 +++++++++++++++++++ > >> 1 file changed, 26 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > >> index ac35491a6f65..ac146c0d628f 100644 > >> --- a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > >> +++ b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml > >> @@ -14,6 +14,7 @@ properties: > >> enum: > >> - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs > >> - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs > >> + - ti,am64-hwspinlock # for K3 AM64x SoCs > >> > >> reg: > >> maxItems: 1 > >> @@ -74,3 +75,28 @@ examples: > >> }; > >> }; > >> }; > >> + > >> + - | > >> + / { > >> + /* K3 AM64x SoCs */ > >> + model = "Texas Instruments K3 AM642 SoC"; > >> + compatible = "ti,am642-evm", "ti,am642"; > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + > >> + bus@f4000 { > >> + compatible = "simple-bus"; > >> + #address-cells = <2>; > >> + #size-cells = <2>; > >> + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ > >> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ > >> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ > >> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>; /* Third peripheral window */ > >> + > >> + spinlock@2a000000 { > > > > Why are you doing the whole hierarchy here? Don't do that. > > I added it because it's integration is slightly different and to help our > downstream consumers. > > > > > In any case, a new compatible doesn't warrant a whole new example, so > > drop the example. > > Yeah ok, will drop the example. > I was just waiting for my build test to pass before pushing this and a few other patches out, will drop the example from the patch here. No need to resend. Thanks, Bjorn > regards > Suman > > > > >> + compatible = "ti,am64-hwspinlock"; > >> + reg = <0x00 0x2a000000 0x00 0x1000>; > >> + #hwlock-cells = <1>; > >> + }; > >> + }; > >> + }; > >> -- > >> 2.29.2 > >> >
On 2/9/21 11:19 AM, Bjorn Andersson wrote: > On Tue 09 Feb 11:09 CST 2021, Suman Anna wrote: > >> Hi Rob, >> >> On 2/9/21 11:00 AM, Rob Herring wrote: >>> On Mon, Jan 25, 2021 at 05:56:52PM -0600, Suman Anna wrote: >>>> Update the existing OMAP HwSpinlock binding to include the info for >>>> AM64x SoCs. There are some minor IP integration differences between >>>> the AM64x SoCs and the previous AM65x and J721E SoC families. A new >>>> example is also added showcasing the difference in the IP's presence >>>> on the interconnect. >>>> >>>> Signed-off-by: Suman Anna <s-anna@ti.com> >>>> --- >>>> .../bindings/hwlock/ti,omap-hwspinlock.yaml | 26 +++++++++++++++++++ >>>> 1 file changed, 26 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >>>> index ac35491a6f65..ac146c0d628f 100644 >>>> --- a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >>>> +++ b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml >>>> @@ -14,6 +14,7 @@ properties: >>>> enum: >>>> - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs >>>> - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs >>>> + - ti,am64-hwspinlock # for K3 AM64x SoCs >>>> >>>> reg: >>>> maxItems: 1 >>>> @@ -74,3 +75,28 @@ examples: >>>> }; >>>> }; >>>> }; >>>> + >>>> + - | >>>> + / { >>>> + /* K3 AM64x SoCs */ >>>> + model = "Texas Instruments K3 AM642 SoC"; >>>> + compatible = "ti,am642-evm", "ti,am642"; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + >>>> + bus@f4000 { >>>> + compatible = "simple-bus"; >>>> + #address-cells = <2>; >>>> + #size-cells = <2>; >>>> + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ >>>> + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ >>>> + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ >>>> + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>; /* Third peripheral window */ >>>> + >>>> + spinlock@2a000000 { >>> >>> Why are you doing the whole hierarchy here? Don't do that. >> >> I added it because it's integration is slightly different and to help our >> downstream consumers. >> >>> >>> In any case, a new compatible doesn't warrant a whole new example, so >>> drop the example. >> >> Yeah ok, will drop the example. >> > > I was just waiting for my build test to pass before pushing this and a > few other patches out, will drop the example from the patch here. No > need to resend. Oops, didn't see this message in time. I have just posted my v2, and you can pick that up directly as I had to remove the last line from the patch description too. Thanks, Suman > > Thanks, > Bjorn > >> regards >> Suman >> >>> >>>> + compatible = "ti,am64-hwspinlock"; >>>> + reg = <0x00 0x2a000000 0x00 0x1000>; >>>> + #hwlock-cells = <1>; >>>> + }; >>>> + }; >>>> + }; >>>> -- >>>> 2.29.2 >>>> >>
diff --git a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml index ac35491a6f65..ac146c0d628f 100644 --- a/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml +++ b/Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml @@ -14,6 +14,7 @@ properties: enum: - ti,omap4-hwspinlock # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs - ti,am654-hwspinlock # for K3 AM65x, J721E and J7200 SoCs + - ti,am64-hwspinlock # for K3 AM64x SoCs reg: maxItems: 1 @@ -74,3 +75,28 @@ examples: }; }; }; + + - | + / { + /* K3 AM64x SoCs */ + model = "Texas Instruments K3 AM642 SoC"; + compatible = "ti,am642-evm", "ti,am642"; + #address-cells = <2>; + #size-cells = <2>; + + bus@f4000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ + <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>; /* Third peripheral window */ + + spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + }; + };
Update the existing OMAP HwSpinlock binding to include the info for AM64x SoCs. There are some minor IP integration differences between the AM64x SoCs and the previous AM65x and J721E SoC families. A new example is also added showcasing the difference in the IP's presence on the interconnect. Signed-off-by: Suman Anna <s-anna@ti.com> --- .../bindings/hwlock/ti,omap-hwspinlock.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)