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From: Zhen Lei <thunder.leizhen@huawei.com>
To: Russell King <rmk+kernel@arm.linux.org.uk>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Will Deacon <will.deacon@arm.com>,
        "Haojian Zhuang" <haojian.zhuang@gmail.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Rob Herring <robh+dt@kernel.org>,
        Wei Xu <xuwei5@hisilicon.com>,
        devicetree <devicetree@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-kernel <linux-kernel@vger.kernel.org>
CC: Zhen Lei <thunder.leizhen@huawei.com>
Subject: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache
 controller
Date: Tue, 12 Jan 2021 09:56:01 +0800
Message-ID: <20210112015602.497-3-thunder.leizhen@huawei.com>
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Add devicetree binding for Hisilicon L3 cache controller.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 .../bindings/arm/hisilicon/l3cache.yaml       | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml
new file mode 100644
index 000000000000000..f411818bad23741
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon L3 cache controller
+
+maintainers:
+  - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+  The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical
+  addresses. The data cached in the L3 outer cache can be operated based on the
+  physical address range or the entire cache.
+
+properties:
+  compatible:
+    items:
+      - const: hisilicon,l3cache
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    l3cache@f302b000 {
+        compatible = "hisilicon,l3cache";
+        reg = <0xf302b000 0x1000>;
+    };
+...