| Message ID | 20200616202417.14376-1-dinguyen@kernel.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/3] dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
Quoting Dinh Nguyen (2020-06-16 13:24:15) > Add the NAND_X_CLK and NAND_ECC_CLK clocks. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next
Quoting Dinh Nguyen (2020-06-16 13:24:16) > And the nand_x_clk and nand_ecc_clk. Make the nand_x_clk be the main > clock that is feeding the NAND IP and correct it's parent to be the > l4_mp_clk. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next
Quoting Dinh Nguyen (2020-06-16 13:24:17) > Preliminary documentation documented the mpu_l2ram_clk, but since then, > the mpu_l2ram_clk is no longer documented. It's now referred to as > mpu_ccu_clk. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Applied to clk-next
diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h index f19cf8ccbdd2..06feca07e08e 100644 --- a/include/dt-bindings/clock/agilex-clock.h +++ b/include/dt-bindings/clock/agilex-clock.h @@ -65,6 +65,8 @@ #define AGILEX_SDMMC_CLK 50 #define AGILEX_SPI_M_CLK 51 #define AGILEX_USB_CLK 52 -#define AGILEX_NUM_CLKS 53 +#define AGILEX_NAND_X_CLK 53 +#define AGILEX_NAND_ECC_CLK 54 +#define AGILEX_NUM_CLKS 55 #endif /* __AGILEX_CLOCK_H */
Add the NAND_X_CLK and NAND_ECC_CLK clocks. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- include/dt-bindings/clock/agilex-clock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)