From patchwork Wed Jan 15 08:58:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong Liang X-Patchwork-Id: 1223227 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=Mydr4I9m; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47yLpr5sMgz9sRX for ; Wed, 15 Jan 2020 19:59:00 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729236AbgAOI6o (ORCPT ); Wed, 15 Jan 2020 03:58:44 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:65318 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729188AbgAOI6n (ORCPT ); Wed, 15 Jan 2020 03:58:43 -0500 X-UUID: ac4081afa8a34e2bbf0cc6981c875a44-20200115 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=U6iKhf6uYPrEgi3REmjZlRMPvQB9C+waid6ttTWHp3c=; b=Mydr4I9mx5azGMIgXkcH8EzodVbCb3N8zbquuoiA0CLiLloVsQSoUQu1ZJR6wzT0+2ugOgCtpq6tc9wfdd5gK+7a6JcoDp+p8DQDQeCMFFrzwjfa3XwPDUqvBcRDqzun6ULKk7qHHZvyYz6h1ztbs2fiFuEgxKqdgKvDaJC1bHs=; X-UUID: ac4081afa8a34e2bbf0cc6981c875a44-20200115 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 958113555; Wed, 15 Jan 2020 16:58:39 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 15 Jan 2020 16:57:40 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 15 Jan 2020 16:58:43 +0800 From: Yong Liang To: , , , , , , , , , , , , CC: , Subject: [PATCH v12 1/4] dt-bindings: mediatek: mt8183: Add #reset-cells Date: Wed, 15 Jan 2020 16:58:25 +0800 Message-ID: <20200115085828.27791-2-yong.liang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200115085828.27791-1-yong.liang@mediatek.com> References: <20200115085828.27791-1-yong.liang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 3E993CFABE8082746CE03459EF01B1928F41185E6C47FF61257C188683AB69782000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: "yong.liang" Add #reset-cells property and update example Signed-off-by: yong.liang Signed-off-by: Jiaxin Yu Reviewed-by: Yingjoe Chen Reviewed-by: Philipp Zabel Reviewed-by: Rob Herring Reviewed-by: Guenter Roeck --- .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 +++++++--- .../reset-controller/mt8183-resets.h | 17 +++++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index fd380eb28df5..ecb9ff784832 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -9,17 +9,21 @@ Required properties: "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 + "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 - reg : Specifies base physical address and size of the registers. Optional properties: - timeout-sec: contains the watchdog timeout in seconds. +- #reset-cells: Should be 1. Example: -wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x18>; +watchdog: watchdog@10007000 { + compatible = "mediatek,mt8183-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; timeout-sec = <10>; + #reset-cells = <1>; }; diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h index 8804e34ebdd4..a1bbd41e0d12 100644 --- a/include/dt-bindings/reset-controller/mt8183-resets.h +++ b/include/dt-bindings/reset-controller/mt8183-resets.h @@ -78,4 +78,21 @@ #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 +#define MT8183_INFRACFG_SW_RST_NUM 128 + +#define MT8183_TOPRGU_MM_SW_RST 1 +#define MT8183_TOPRGU_MFG_SW_RST 2 +#define MT8183_TOPRGU_VENC_SW_RST 3 +#define MT8183_TOPRGU_VDEC_SW_RST 4 +#define MT8183_TOPRGU_IMG_SW_RST 5 +#define MT8183_TOPRGU_MD_SW_RST 7 +#define MT8183_TOPRGU_CONN_SW_RST 9 +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 +#define MT8183_TOPRGU_IPU0_SW_RST 14 +#define MT8183_TOPRGU_IPU1_SW_RST 15 +#define MT8183_TOPRGU_AUDIO_SW_RST 17 +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 + +#define MT8183_TOPRGU_SW_RST_NUM 19 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */