From patchwork Fri Nov 15 14:59:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud POULIQUEN X-Patchwork-Id: 1195697 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=st.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=st.com header.i=@st.com header.b="YYJIzWy2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47F1jL3l1bz9sP6 for ; Sat, 16 Nov 2019 01:59:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727485AbfKOO7t (ORCPT ); Fri, 15 Nov 2019 09:59:49 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:60844 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727380AbfKOO7t (ORCPT ); Fri, 15 Nov 2019 09:59:49 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xAFEvJEH014335; Fri, 15 Nov 2019 15:59:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=STMicroelectronics; bh=iNjEFxhb9aKBGFWEXfbIOQoBZPywYOAPMDV4+3r80sA=; b=YYJIzWy2U6ZcfnWC3oJL+b48NKHNNCDDA/Vl0Rv1lWdlsghNk9mCmhg1xbjyUyaqH2cl 4XWwX8i6LMpnmVLFFUslV4Vcu4onfhyoatH+l8Ms8azZ1PbuMcpoPqGuXNIn9bqnqmZA iylPnWiN/tZx0EUCYX4N5cYGNd018snypeiJeegJcdaSuU0zJJypoZ+E9+zBjOXNIrS8 7tu8MA8hinTAEW4XJLMM+YlJ+3uduVYO7BOrG9AiJv63iGk5ZjwdbY3C82Cajrvpr4+2 BGSfwBLa75gS72TJH23e9rRB4ujrQSFbfblbKvcaJSvfbyEznKgC5tpJ6PuAdRnKQ182 Gg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2w7psk4sj7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2019 15:59:32 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4282D10002A; Fri, 15 Nov 2019 15:59:32 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node1.st.com [10.75.127.7]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2BF2D2C01FC; Fri, 15 Nov 2019 15:59:32 +0100 (CET) Received: from localhost (10.75.127.47) by SFHDAG3NODE1.st.com (10.75.127.7) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 15 Nov 2019 15:59:31 +0100 From: Arnaud Pouliquen To: Rob Herring , Mark Rutland , Alexandre Torgue , Jassi Brar CC: , , , , Fabien Dessenne , Arnaud Pouliquen Subject: [PATCH] dt-bindings: mailbox: convert stm32-ipcc to json-schema Date: Fri, 15 Nov 2019 15:59:15 +0100 Message-ID: <20191115145915.6887-1-arnaud.pouliquen@st.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG3NODE1.st.com (10.75.127.7) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95, 18.0.572 definitions=2019-11-15_04:2019-11-15, 2019-11-15 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the STM32 IPCC bindings to DT schema format using json-schema Signed-off-by: Arnaud Pouliquen --- .../bindings/mailbox/st,stm32-ipcc.yaml | 91 +++++++++++++++++++ .../bindings/mailbox/stm32-ipcc.txt | 47 ---------- 2 files changed, 91 insertions(+), 47 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml new file mode 100644 index 000000000000..6843d51d96da --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STM32 GPIO and Pin Mux/Config controller + +description: | + The IPCC block provides a non blocking signaling mechanism to post and + retrieve messages in an atomic way between two processors. + It provides the signaling for N bidirectionnal channels. The number of + channels (N) can be read from a dedicated register. + +maintainers: + - Fabien Dessenne + - Arnaud Pouliquen + +properties: + compatible: + const: st,stm32mp1-ipcc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + items: + - description: rx channel occupied + - description: tx channel free + - description: wakeup source + minItems: 2 + maxItems: 3 + + interrupt-names: + items: + enums: [ rx, tx, wakeup ] + minItems: 2 + maxItems: 3 + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enables wake up of host system on wakeup IRQ assertion. + + "#mbox-cells": + const: 1 + + st,proc-id: + description: Processor id using the mailbox (0 or 1) + allOf: + - minimum: 0 + - maximum: 1 + - default: 0 + +required: + - compatible + - reg + - st,proc-id + - clocks + - interrupt-names + - "#mbox-cells" + +oneOf: + - required: + - interrupts + - required: + - interrupts-extended + +additionalProperties: false + +examples: + - | + #include + #include + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, + <&intc GIC_SPI 101 IRQ_TYPE_NONE>, + <&aiec 62 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc_clk IPCC>; + wakeup-source; + }; + +... diff --git a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt b/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt deleted file mode 100644 index 1d2b7fee7b85..000000000000 --- a/Documentation/devicetree/bindings/mailbox/stm32-ipcc.txt +++ /dev/null @@ -1,47 +0,0 @@ -* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller) - -The IPCC block provides a non blocking signaling mechanism to post and -retrieve messages in an atomic way between two processors. -It provides the signaling for N bidirectionnal channels. The number of channels -(N) can be read from a dedicated register. - -Required properties: -- compatible: Must be "st,stm32mp1-ipcc" -- reg: Register address range (base address and length) -- st,proc-id: Processor id using the mailbox (0 or 1) -- clocks: Input clock -- interrupt-names: List of names for the interrupts described by the interrupt - property. Must contain the following entries: - - "rx" - - "tx" - - "wakeup" -- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel - free" and "system wakeup". -- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1. - The data contained in the mbox specifier of the "mboxes" - property in the client node is the mailbox channel index. - -Optional properties: -- wakeup-source: Flag to indicate whether this device can wake up the system - - - -Example: - ipcc: mailbox@4c001000 { - compatible = "st,stm32mp1-ipcc"; - #mbox-cells = <1>; - reg = <0x4c001000 0x400>; - st,proc-id = <0>; - interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, - <&intc GIC_SPI 101 IRQ_TYPE_NONE>, - <&aiec 62 1>; - interrupt-names = "rx", "tx", "wakeup"; - clocks = <&rcc_clk IPCC>; - wakeup-source; - } - -Client: - mbox_test { - ... - mboxes = <&ipcc 0>, <&ipcc 1>; - };