From patchwork Mon Nov 4 16:38:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 1189041 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 476JQc73g2z9sPL for ; Tue, 5 Nov 2019 03:38:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728648AbfKDQiq (ORCPT ); Mon, 4 Nov 2019 11:38:46 -0500 Received: from foss.arm.com ([217.140.110.172]:46772 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727861AbfKDQiq (ORCPT ); Mon, 4 Nov 2019 11:38:46 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FB9E328; Mon, 4 Nov 2019 08:38:45 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 978AE3F71A; Mon, 4 Nov 2019 08:38:44 -0800 (PST) From: Andrew Murray To: Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org Subject: [PATCH v1 1/7] PCI: dt: Add legacy PCI IRQ defines Date: Mon, 4 Nov 2019 16:38:15 +0000 Message-Id: <20191104163834.8932-2-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191104163834.8932-1-andrew.murray@arm.com> References: <20191104163834.8932-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PCI devices can trigger interrupts via 4 physical/virtual lines known as INTA, INTB, INTC or INTD. Due to interrupt swizzling it is often required to describe the interrupt mapping in the device tree. Let's add a define for each type to improve device tree clarity. Signed-off-by: Andrew Murray Acked-by: Rob Herring --- include/dt-bindings/interrupt-controller/irq.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h index 9e3d183e1381..f9063fd661cd 100644 --- a/include/dt-bindings/interrupt-controller/irq.h +++ b/include/dt-bindings/interrupt-controller/irq.h @@ -17,4 +17,12 @@ #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 +/* Legacy PCI IRQ lines */ +#define IRQ_INTA 1 +#define IRQ_INTB 2 +#define IRQ_INTC 3 +#define IRQ_INTD 4 + +#define IRQ_INT_ALL 7 + #endif