| Message ID | 20190827085302.5197-12-jiaxun.yang@flygoat.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Modernize Loongson64 Machine | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > Prepare for later dts. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++ > .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++ > 2 files changed, 102 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml > create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > new file mode 100644 > index 000000000000..410d896a0078 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > @@ -0,0 +1,38 @@ > +# SPDX-License-Identifier: GPL-2.0 Dual license for new bindings please: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Loongson CPUs bindings > + > +maintainers: > + - Jiaxun Yang <jiaxun.yang@flygoat.com> > + > +description: |+ > + The device tree allows to describe the layout of CPUs in a system through > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") > + defining properties for every cpu. > + > + Bindings for CPU nodes follow the Devicetree Specification, available from: > + > + https://www.devicetree.org/specifications/ > + > +properties: > + reg: > + maxItems: 1 > + description: | > + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. Is this definition specific to Loongson CPUs or all MIPS? I would expect to see a common MIPS CPU schema with these compatibles listed there. > + > + compatible: > + enum: > + - loongson,gs464 > + - loongson,gs464e > + - loongson,gs264 > + - loongson,gs464v > + > +required: > + - device_type > + - reg > + - compatible > +... > diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > new file mode 100644 > index 000000000000..181881a9f4a9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > @@ -0,0 +1,64 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek SoC based Platforms Device Tree Bindings MediaTek SoC? > + > +maintainers: > + - Jiaxun Yang <jiaxun.yang@flygoat.com> > +description: | > + Devices with a Loongson CPU shall have the following properties. > + > +properties: > + $nodename: > + const: '/' > + compatible: > + oneOf: > + > + - description: Loongson 3A1000 + RS780E 1Way > + items: > + - const: loongson,ls3a1000-780e-1way > + > + - description: Loongson 3A1000 + RS780E 2Way > + items: > + - const: loongson,ls3a1000-780e-2way > + > + - description: Loongson 3A1000 + RS780E 4Way > + items: > + - const: loongson,ls3a1000-780e-4way > + > + - description: Loongson 3B1000/1500 + RS780E 1Way > + items: > + - const: loongson,ls3b-780e-1way > + > + - description: Loongson 3B1000/1500 + RS780E 2Way > + items: > + - const: loongson,ls3b-780e-2way > + > + - description: Loongson 3A2000 + RS780E 1Way > + items: > + - const: loongson,ls3a2000-780e-1way > + > + - description: Loongson 3A2000 + RS780E 2Way > + items: > + - const: loongson,ls3a2000-780e-2way > + > + - description: Loongson 3A2000 + RS780E 4Way > + items: > + - const: loongson,ls3a2000-780e-4way > + > + - description: Loongson 3A3000 + RS780E 1Way > + items: > + - const: loongson,ls3a3000-780e-1way > + > + - description: Loongson 3A3000 + RS780E 2Way > + items: > + - const: loongson,ls3a3000-780e-2way > + > + - description: Loongson 3A3000 + RS780E 4Way > + items: > + - const: loongson,ls3a3000-780e-4way > + > +... > -- > 2.22.0 >
On 2019/8/27 下午8:45, Rob Herring wrote: > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: >> Prepare for later dts. >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> --- >> .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++ >> .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++ >> 2 files changed, 102 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml >> create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml >> >> diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml >> new file mode 100644 >> index 000000000000..410d896a0078 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml >> @@ -0,0 +1,38 @@ >> +# SPDX-License-Identifier: GPL-2.0 > Dual license for new bindings please: > > (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Loongson CPUs bindings >> + >> +maintainers: >> + - Jiaxun Yang <jiaxun.yang@flygoat.com> >> + >> +description: |+ >> + The device tree allows to describe the layout of CPUs in a system through >> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") >> + defining properties for every cpu. >> + >> + Bindings for CPU nodes follow the Devicetree Specification, available from: >> + >> + https://www.devicetree.org/specifications/ >> + >> +properties: >> + reg: >> + maxItems: 1 >> + description: | >> + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. > Is this definition specific to Loongson CPUs or all MIPS? Currently it's specific to Loongson CPU only, as other processors may using different method to express CPU map. Different from Arm, MIPS family of processors seems less uniform and have their own designs. For this point, we'd better ask Paul's opinion. -- Jiaxun Yang
Hi guys, On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote: > On 2019/8/27 下午8:45, Rob Herring wrote: > > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > > > new file mode 100644 > > > index 000000000000..410d896a0078 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > > > @@ -0,0 +1,38 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > Dual license for new bindings please: > > > > (GPL-2.0-only OR BSD-2-Clause) > > > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Loongson CPUs bindings > > > + > > > +maintainers: > > > + - Jiaxun Yang <jiaxun.yang@flygoat.com> > > > + > > > +description: |+ > > > + The device tree allows to describe the layout of CPUs in a system through > > > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") > > > + defining properties for every cpu. > > > + > > > + Bindings for CPU nodes follow the Devicetree Specification, available from: > > > + > > > + https://www.devicetree.org/specifications/ > > > + > > > +properties: > > > + reg: > > > + maxItems: 1 > > > + description: | > > > + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. > > Is this definition specific to Loongson CPUs or all MIPS? > > Currently it's specific to Loongson CPU only, as other processors may using > different method to express CPU map. > > Different from Arm, MIPS family of processors seems less uniform and have > their own designs. > > For this point, we'd better ask Paul's opinion. In general on MIPS we detect CPU properties at runtime from coprocessor 0 registers & similar sources of information, so there's not really a need to specify anything about the CPU in devicetree. For example here you say yourself that the value for this property can be read from EBase.CPUNum - so why specify it in DT? Thanks, Paul
On 2019/8/28 上午4:41, Paul Burton wrote: > Hi guys, > > On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote: >> On 2019/8/27 下午8:45, Rob Herring wrote: >>> On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: >>>> diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml >>>> new file mode 100644 >>>> index 000000000000..410d896a0078 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml >>>> @@ -0,0 +1,38 @@ >>>> +# SPDX-License-Identifier: GPL-2.0 >>> Dual license for new bindings please: >>> >>> (GPL-2.0-only OR BSD-2-Clause) >>> >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Loongson CPUs bindings >>>> + >>>> +maintainers: >>>> + - Jiaxun Yang <jiaxun.yang@flygoat.com> >>>> + >>>> +description: |+ >>>> + The device tree allows to describe the layout of CPUs in a system through >>>> + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") >>>> + defining properties for every cpu. >>>> + >>>> + Bindings for CPU nodes follow the Devicetree Specification, available from: >>>> + >>>> + https://www.devicetree.org/specifications/ >>>> + >>>> +properties: >>>> + reg: >>>> + maxItems: 1 >>>> + description: | >>>> + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. >>> Is this definition specific to Loongson CPUs or all MIPS? >> Currently it's specific to Loongson CPU only, as other processors may using >> different method to express CPU map. >> >> Different from Arm, MIPS family of processors seems less uniform and have >> their own designs. >> >> For this point, we'd better ask Paul's opinion. > In general on MIPS we detect CPU properties at runtime from coprocessor > 0 registers & similar sources of information, so there's not really a > need to specify anything about the CPU in devicetree. For example here > you say yourself that the value for this property can be read from > EBase.CPUNum - so why specify it in DT? Hi Paul, CPU itself doesn't have to expressed by DT, but other nodes (like NUMA) will use CPU Node to determine the physical core. Also CPU Node can be used to express the total number of CPUs. We need this property to bind a CPU Node to a fixed core. Or we'd better describe "reg" as "Physical Core ID" rather than specify "EBase.CPUNum"? -- Jiaxun Yang > > Thanks, > Paul
On Tue, Aug 27, 2019 at 9:41 PM Paul Burton <paul.burton@mips.com> wrote: > > Hi guys, > > On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote: > > On 2019/8/27 下午8:45, Rob Herring wrote: > > > On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > > > diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > > > > new file mode 100644 > > > > index 000000000000..410d896a0078 > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml > > > > @@ -0,0 +1,38 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > Dual license for new bindings please: > > > > > > (GPL-2.0-only OR BSD-2-Clause) > > > > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Loongson CPUs bindings > > > > + > > > > +maintainers: > > > > + - Jiaxun Yang <jiaxun.yang@flygoat.com> > > > > + > > > > +description: |+ > > > > + The device tree allows to describe the layout of CPUs in a system through > > > > + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") > > > > + defining properties for every cpu. > > > > + > > > > + Bindings for CPU nodes follow the Devicetree Specification, available from: > > > > + > > > > + https://www.devicetree.org/specifications/ > > > > + > > > > +properties: > > > > + reg: > > > > + maxItems: 1 > > > > + description: | > > > > + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. > > > Is this definition specific to Loongson CPUs or all MIPS? > > > > Currently it's specific to Loongson CPU only, as other processors may using > > different method to express CPU map. > > > > Different from Arm, MIPS family of processors seems less uniform and have > > their own designs. > > > > For this point, we'd better ask Paul's opinion. > > In general on MIPS we detect CPU properties at runtime from coprocessor > 0 registers & similar sources of information, so there's not really a > need to specify anything about the CPU in devicetree. We thought the same thing initially for Arm... Mostly what is in DT is not what is discoverable. Are clock speeds, power domains, low power states, etc. all discoverable? > For example here > you say yourself that the value for this property can be read from > EBase.CPUNum - so why specify it in DT? To map DT nodes to cores? Rob
Hi Rob, On Mon, Sep 02, 2019 at 03:50:47PM +0100, Rob Herring wrote: > > In general on MIPS we detect CPU properties at runtime from coprocessor > > 0 registers & similar sources of information, so there's not really a > > need to specify anything about the CPU in devicetree. > > We thought the same thing initially for Arm... Mostly what is in DT is > not what is discoverable. Are clock speeds, power domains, low power > states, etc. all discoverable? No, that's a good point - clocks etc may need to be specified in DT. I just don't see any of that in this patchset - it appears all that is specified is cache sizes which we already detect. So in this case I don't see a need for including CPUs in DT at all. Jiaxun - did you add all this information to DT to avoid the "cacheinfo: Unable to detect cache hierarchy for CPU" messages during boot? If so that should be fixed by commit b8bea8a5e5d9 ("mips: fix cacheinfo"). If not, could you describe why the CPU nodes are needed here? Thanks, Paul
On Tue, Sep 3, 2019 at 5:08 PM Paul Burton <paul.burton@mips.com> wrote: > > Hi Rob, > > On Mon, Sep 02, 2019 at 03:50:47PM +0100, Rob Herring wrote: > > > In general on MIPS we detect CPU properties at runtime from coprocessor > > > 0 registers & similar sources of information, so there's not really a > > > need to specify anything about the CPU in devicetree. > > > > We thought the same thing initially for Arm... Mostly what is in DT is > > not what is discoverable. Are clock speeds, power domains, low power > > states, etc. all discoverable? > > No, that's a good point - clocks etc may need to be specified in DT. I > just don't see any of that in this patchset - it appears all that is > specified is cache sizes which we already detect. So in this case I > don't see a need for including CPUs in DT at all. > > Jiaxun - did you add all this information to DT to avoid the "cacheinfo: > Unable to detect cache hierarchy for CPU" messages during boot? If so > that should be fixed by commit b8bea8a5e5d9 ("mips: fix cacheinfo"). If > not, could you describe why the CPU nodes are needed here? Yes, this can avoid "cacheinfo: Unable to detect cache hierarchy for CPU". In our own git repository we have already reverted commit b8bea8a5e5d9 ("mips: fix cacheinfo") Huacai > > Thanks, > Paul
diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml new file mode 100644 index 000000000000..410d896a0078 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/cpus.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson CPUs bindings + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> + +description: |+ + The device tree allows to describe the layout of CPUs in a system through + the "cpus" node, which in turn contains a number of subnodes (ie "cpu") + defining properties for every cpu. + + Bindings for CPU nodes follow the Devicetree Specification, available from: + + https://www.devicetree.org/specifications/ + +properties: + reg: + maxItems: 1 + description: | + Physical ID of a CPU, Can be read from CP0 EBase.CPUNum. + + compatible: + enum: + - loongson,gs464 + - loongson,gs464e + - loongson,gs264 + - loongson,gs464v + +required: + - device_type + - reg + - compatible +... diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml new file mode 100644 index 000000000000..181881a9f4a9 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/loongson/devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC based Platforms Device Tree Bindings + +maintainers: + - Jiaxun Yang <jiaxun.yang@flygoat.com> +description: | + Devices with a Loongson CPU shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Loongson 3A1000 + RS780E 1Way + items: + - const: loongson,ls3a1000-780e-1way + + - description: Loongson 3A1000 + RS780E 2Way + items: + - const: loongson,ls3a1000-780e-2way + + - description: Loongson 3A1000 + RS780E 4Way + items: + - const: loongson,ls3a1000-780e-4way + + - description: Loongson 3B1000/1500 + RS780E 1Way + items: + - const: loongson,ls3b-780e-1way + + - description: Loongson 3B1000/1500 + RS780E 2Way + items: + - const: loongson,ls3b-780e-2way + + - description: Loongson 3A2000 + RS780E 1Way + items: + - const: loongson,ls3a2000-780e-1way + + - description: Loongson 3A2000 + RS780E 2Way + items: + - const: loongson,ls3a2000-780e-2way + + - description: Loongson 3A2000 + RS780E 4Way + items: + - const: loongson,ls3a2000-780e-4way + + - description: Loongson 3A3000 + RS780E 1Way + items: + - const: loongson,ls3a3000-780e-1way + + - description: Loongson 3A3000 + RS780E 2Way + items: + - const: loongson,ls3a3000-780e-2way + + - description: Loongson 3A3000 + RS780E 4Way + items: + - const: loongson,ls3a3000-780e-4way + +...
Prepare for later dts. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- .../bindings/mips/loongson/cpus.yaml | 38 +++++++++++ .../bindings/mips/loongson/devices.yaml | 64 +++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/loongson/cpus.yaml create mode 100644 Documentation/devicetree/bindings/mips/loongson/devices.yaml