From patchwork Wed May 29 21:13:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1107402 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="XsCNoGuj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45Dk4Y61Xdz9s3l for ; Thu, 30 May 2019 07:14:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726418AbfE2VOx (ORCPT ); Wed, 29 May 2019 17:14:53 -0400 Received: from esa4.hgst.iphmx.com ([216.71.154.42]:26075 "EHLO esa4.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726043AbfE2VOx (ORCPT ); Wed, 29 May 2019 17:14:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1559164492; x=1590700492; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=29osV+2RDGf1LHK2n5eg5QB1HBqM11BN+lKruv8f5mA=; b=XsCNoGuj2pXvRe2yXUwQGd1nQUgHBXTXsO+47Z0EH0Bwn4032/CXCUBG 6UL4uJCt/6Giag+dBEVCQcXaWtjYmzZSlXsTGi9hZ+OPaG9VFcK48lg0H cPf1cT2CZj4DOG5uv3N44TtwLL1QQjTrzfooDcGfYf9AdcdzXHqsNDIN2 JdBKeHPzgtGtdT1taJcFu3nzXTjJ94HFhfU5WCWAo8wQU97WOqPp/WqBT Ahh1O3LtQVR5+dbZtqn4HCnBPd+oD6tIrBTw7GfJVzGmSDVG91eLCLXwL ZQofJxyjbbgNU75Un8BV/4AIWZb+CG1EKZCWVuY/nYBhjcAh+dqu3oalP w==; X-IronPort-AV: E=Sophos;i="5.60,527,1549900800"; d="scan'208";a="109341707" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 May 2019 05:14:52 +0800 IronPort-SDR: L1Q0WWyWyEm2w5NI43kJzZKjI9C9hWMIVD7+55XNjSNOKfAiOF4878v9iZvRLBUg3D31Vd6oy4 Zl/DtEh/CVaDK4mGYvgH2VmzhXxroblZvh+KxCCApvUmVjxCDfbsa6mL+FAcAGOi+SWRg6pt0+ 8u/aqTGuCc0jprRJneGOJ9N8aJE4AfkWfoXCw4ptyG0OQD1EE0ub96RGEVFjfl1SGYwmjapQck ahar3NDBKaQ8rHQ1TI1YI7T3w6y+Hcfu81zJGLwoSXK+NMxHsBttIDfvBSbaq8jPIdxvCNwfTD c9i1yvauzd43GW4ctSj4HHSH Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 29 May 2019 13:52:23 -0700 IronPort-SDR: bPIiVoyeFfUCPVUFL2xj+HhRezN9xnE/X3xkbSBVRHM/pB/p0s+4JIYQ9o/RsJdGZS2PjwOUC0 ZHB9mrd8LKMcoLdd4/qW/TxJoyQoteOM9FzLlEaygQkGJj+GfQuFNbUxH5kfEmy0CatjE9V9K8 7YguOaRB+6I4pnmFNm8QOHpG44aKOoq7WVrGrLen7HioJiwSDxuHV1790nFHzggITZ21vt/cVx JB9bUldYTntPtdkUV+KaV217TzFWfxdtW/k/TlNt/RC5pbpx7a0QjSpvPYEqs6AgdOS8d/gzws T6k= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 29 May 2019 14:14:51 -0700 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Sudeep Holla , Rob Herring , Albert Ou , Anup Patel , Catalin Marinas , "David S. Miller" , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , Linus Walleij , linux-riscv@lists.infradead.org, Mark Rutland , Mauro Carvalho Chehab , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , Paul Walmsley , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Thomas Gleixner , Will Deacon , Russell King , linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 2/7] dt-binding: cpu-topology: Move cpu-map to a common binding. Date: Wed, 29 May 2019 14:13:35 -0700 Message-Id: <20190529211340.17087-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190529211340.17087-1-atish.patra@wdc.com> References: <20190529211340.17087-1-atish.patra@wdc.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org cpu-map binding can be used to described cpu topology for both RISC-V & ARM. It makes more sense to move the binding to document to a common place. The relevant discussion can be found here. https://lkml.org/lkml/2018/11/6/19 Signed-off-by: Atish Patra Reviewed-by: Sudeep Holla Reviewed-by: Rob Herring --- .../topology.txt => cpu/cpu-topology.txt} | 82 +++++++++++++++---- 1 file changed, 66 insertions(+), 16 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (86%) diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/cpu/cpu-topology.txt similarity index 86% rename from Documentation/devicetree/bindings/arm/topology.txt rename to Documentation/devicetree/bindings/cpu/cpu-topology.txt index 3b8febb46dad..069addccab14 100644 --- a/Documentation/devicetree/bindings/arm/topology.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-topology.txt @@ -1,12 +1,12 @@ =========================================== -ARM topology binding description +CPU topology binding description =========================================== =========================================== 1 - Introduction =========================================== -In an ARM system, the hierarchy of CPUs is defined through three entities that +In a SMP system, the hierarchy of CPUs is defined through three entities that are used to describe the layout of physical CPUs in the system: - socket @@ -14,9 +14,6 @@ are used to describe the layout of physical CPUs in the system: - core - thread -The cpu nodes (bindings defined in [1]) represent the devices that -correspond to physical CPUs and are to be mapped to the hierarchy levels. - The bottom hierarchy level sits at core or thread level depending on whether symmetric multi-threading (SMT) is supported or not. @@ -25,33 +22,31 @@ threads existing in the system and map to the hierarchy level "thread" above. In systems where SMT is not supported "cpu" nodes represent all cores present in the system and map to the hierarchy level "core" above. -ARM topology bindings allow one to associate cpu nodes with hierarchical groups +CPU topology bindings allow one to associate cpu nodes with hierarchical groups corresponding to the system hierarchy; syntactically they are defined as device tree nodes. -The remainder of this document provides the topology bindings for ARM, based -on the Devicetree Specification, available from: +Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be +used for any other architecture as well. -https://www.devicetree.org/specifications/ +The cpu nodes, as per bindings defined in [4], represent the devices that +correspond to physical CPUs and are to be mapped to the hierarchy levels. -If not stated otherwise, whenever a reference to a cpu node phandle is made its -value must point to a cpu node compliant with the cpu node bindings as -documented in [1]. A topology description containing phandles to cpu nodes that are not compliant -with bindings standardized in [1] is therefore considered invalid. +with bindings standardized in [4] is therefore considered invalid. =========================================== 2 - cpu-map node =========================================== -The ARM CPU topology is defined within the cpu-map node, which is a direct +The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct child of the cpus node and provides a container where the actual topology nodes are listed. - cpu-map node - Usage: Optional - On ARM SMP systems provide CPUs topology to the OS. - ARM uniprocessor systems do not require a topology + Usage: Optional - On SMP systems provide CPUs topology to the OS. + Uniprocessor systems do not require a topology description and therefore should not define a cpu-map node. @@ -494,8 +489,63 @@ cpus { }; }; +Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system) + +{ + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + ... + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU1>; + }; + core1 { + cpu = <&CPU2>; + }; + core2 { + cpu0 = <&CPU2>; + }; + core3 { + cpu0 = <&CPU3>; + }; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x1>; + } + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x2>; + } + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x3>; + } + CPU4: cpu@4 { + device_type = "cpu"; + compatible = "sifive,rocket0", "riscv"; + reg = <0x4>; + } + } +}; =============================================================================== [1] ARM Linux kernel documentation Documentation/devicetree/bindings/arm/cpus.yaml [2] Devicetree NUMA binding description Documentation/devicetree/bindings/numa.txt +[3] RISC-V Linux kernel documentation + Documentation/devicetree/bindings/riscv/cpus.txt +[4] https://www.devicetree.org/specifications/