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Tue, 30 Apr 2019 19:52:37 +0000 From: Peter Rosin To: "linux-kernel@vger.kernel.org" CC: Pankaj Bansal , Peter Rosin , Rob Herring , Mark Rutland , "devicetree@vger.kernel.org" Subject: [PATCH 1/2] dt-bindings: add register based devices' mux controller DT bindings Thread-Topic: [PATCH 1/2] dt-bindings: add register based devices' mux controller DT bindings Thread-Index: AQHU/45DqApaDcj32EqoEwOk29aykg== Date: Tue, 30 Apr 2019 19:52:37 +0000 Message-ID: <20190430195226.8965-2-peda@axentia.se> References: <20190430195226.8965-1-peda@axentia.se> In-Reply-To: <20190430195226.8965-1-peda@axentia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.11.0 x-originating-ip: [213.112.138.100] x-clientproxiedby: HE1P189CA0028.EURP189.PROD.OUTLOOK.COM (2603:10a6:7:53::41) To AM0PR02MB4563.eurprd02.prod.outlook.com (2603:10a6:208:ec::33) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peda@axentia.se; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: fe190814-674b-4ff8-1344-08d6cda56565 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1102; SCL:1; SRVR:AM0PR02MB4609; H:AM0PR02MB4563.eurprd02.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: axentia.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /Bzx7HobrJhSE+/70ctZui5ukmW/nhS0Zea/FIl2hnwlw1YwmDMeRx5IObfn+yy2mXBbfWmlBsLp/KqIFGMpnzRKw6uMt0mtLiMJRShuMfnhaa0Rzq7s3J0WFBuqgjpzy4RukKAesfN1IUyt29xoOStXqVvj02KQBqCtCq5QorZ4J5n4wWj/sViU8qThhybAYx86mAfaOBZ05aADNNaebkdkKdGohUBj8tSGgcxlYmgmT6uwkysxwyJfFz4VN3IX3LUuo2I543qIOL9eug5Qs2UZXxrWWbplutA/tlLeEaYdapweouECvnUYxhFRPa+QWDh+d72H0jodzUCb6eH2e/cY1WpxDs+NfLgFht3iRJILAtrGlOMVVy6K9EC/t7S49cRtU9CqRvnwGj90qx05vwpfu2z2rI3pAtLSQ+Q3Xuk= MIME-Version: 1.0 X-OriginatorOrg: axentia.se X-MS-Exchange-CrossTenant-Network-Message-Id: fe190814-674b-4ff8-1344-08d6cda56565 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Apr 2019 19:52:37.6526 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4ee68585-03e1-4785-942a-df9c1871a234 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR02MB4609 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pankaj Bansal This adds device tree binding documentation for generic register based multiplexer controlled by a bitfields in a parent device's register range. since MMIO mux is a special case of generic register based mux, the MMIO mux bindings have been subsumed in these bindings. Signed-off-by: Pankaj Bansal Signed-off-by: Peter Rosin --- Documentation/devicetree/bindings/mux/mmio-mux.txt | 60 ---------- Documentation/devicetree/bindings/mux/reg-mux.txt | 129 +++++++++++++++++++++ 2 files changed, 129 insertions(+), 60 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mux/mmio-mux.txt create mode 100644 Documentation/devicetree/bindings/mux/reg-mux.txt diff --git a/Documentation/devicetree/bindings/mux/mmio-mux.txt b/Documentation/devicetree/bindings/mux/mmio-mux.txt deleted file mode 100644 index a9bfb4d8b6ac..000000000000 --- a/Documentation/devicetree/bindings/mux/mmio-mux.txt +++ /dev/null @@ -1,60 +0,0 @@ -MMIO register bitfield-based multiplexer controller bindings - -Define register bitfields to be used to control multiplexers. The parent -device tree node must be a syscon node to provide register access. - -Required properties: -- compatible : "mmio-mux" -- #mux-control-cells : <1> -- mux-reg-masks : an array of register offset and pre-shifted bitfield mask - pairs, each describing a single mux control. -* Standard mux-controller bindings as decribed in mux-controller.txt - -Optional properties: -- idle-states : if present, the state the muxes will have when idle. The - special state MUX_IDLE_AS_IS is the default. - -The multiplexer state of each multiplexer is defined as the value of the -bitfield described by the corresponding register offset and bitfield mask pair -in the mux-reg-masks array, accessed through the parent syscon. - -Example: - - syscon { - compatible = "syscon"; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - - mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ - <0x3 0x40>, /* 1: reg 0x3, bit 6 */ - idle-states = , <0>; - }; - }; - - video-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - - ports { - /* inputs 0..3 */ - port@0 { - reg = <0>; - }; - port@1 { - reg = <1>; - }; - port@2 { - reg = <2>; - }; - port@3 { - reg = <3>; - }; - - /* output */ - port@4 { - reg = <4>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mux/reg-mux.txt b/Documentation/devicetree/bindings/mux/reg-mux.txt new file mode 100644 index 000000000000..4afd7ba73d60 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/reg-mux.txt @@ -0,0 +1,129 @@ +Generic register bitfield-based multiplexer controller bindings + +Define register bitfields to be used to control multiplexers. The parent +device tree node must be a device node to provide register r/w access. + +Required properties: +- compatible : should be one of + "reg-mux" : if parent device of mux controller is not syscon device + "mmio-mux" : if parent device of mux controller is syscon device +- #mux-control-cells : <1> +- mux-reg-masks : an array of register offset and pre-shifted bitfield mask + pairs, each describing a single mux control. +* Standard mux-controller bindings as decribed in mux-controller.txt + +Optional properties: +- idle-states : if present, the state the muxes will have when idle. The + special state MUX_IDLE_AS_IS is the default. + +The multiplexer state of each multiplexer is defined as the value of the +bitfield described by the corresponding register offset and bitfield mask +pair in the mux-reg-masks array. + +Example 1: +The parent device of mux controller is not a syscon device. + +&i2c0 { + fpga@66 { // fpga connected to i2c + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */ + }; + }; +}; + +mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@8 { + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + }; + + .. + .. +}; + +mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + .. + .. +}; + +Example 2: +The parent device of mux controller is syscon device. + +syscon { + compatible = "syscon"; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */ + <0x3 0x40>, /* 1: reg 0x3, bit 6 */ + idle-states = , <0>; + }; +}; + +video-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + + ports { + /* inputs 0..3 */ + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + port@3 { + reg = <3>; + }; + + /* output */ + port@4 { + reg = <4>; + }; + }; +};