From patchwork Thu Mar 21 17:17:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1060306 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="Kr1Bi0yt"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44QD6H3W4bz9s6w for ; Fri, 22 Mar 2019 04:19:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728752AbfCURSS (ORCPT ); Thu, 21 Mar 2019 13:18:18 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:33435 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728748AbfCURSS (ORCPT ); Thu, 21 Mar 2019 13:18:18 -0400 Received: by mail-pg1-f194.google.com with SMTP id b12so4666919pgk.0 for ; Thu, 21 Mar 2019 10:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5VTcVo1Chs4XGa35tec1xGg2FL/05IcVUKqdSKt+U9Q=; b=Kr1Bi0ytzlIExrHApFqy1i2jPUQf5/OokIJmBfy88t6HmBn28AzgN6842rJUZ2wmQx LCQ0JbLwZpGjnZIYqJaa2e5V2i/f+jtne9UBW62i8YsOzXXWUy91ZxTlU4Em4XNQ2krG Z3n2muBhDqKmlKuIu8zh5BF2z13WJk+9N3Zek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5VTcVo1Chs4XGa35tec1xGg2FL/05IcVUKqdSKt+U9Q=; b=FexJsYjO2QhM+OWSfKYEQ5pvNbbQLF1zxDcVtkQv2Zx6hjqibzkoik4uBuBwggpqsy +/JBaYtltbQGajq5n7+xUlhTa3sb3MWTqYxe4FBDTLT4wTzAE9hnjUm0jGbGbvGK1SYR Bkq100rNn55o2IBVbJj9OqYN1Y5/0A2uTLWd86RGI7yzsWQ4hM6KRrYbBhq+DYodTt2F AAVagdCOmynZxn2mH1CHBUWh6e+QPYexTMynstrlHX3os/XZjgMe1ymKMA6VqkZhQhm0 h0vFtdnfHcMHhLwI2OtGtvEeRFyouxwAT8vtsBULYofrHkbNVWKIxQThEmMLzb+AE0Y5 I2gQ== X-Gm-Message-State: APjAAAVhB9jx8VCxo62vJ1h5Yvc7qerj7PPwa3TR5bYrRu0hR9Fmndxt XywNVL75mc3SWcTrXVnNa6PQXQ== X-Google-Smtp-Source: APXvYqwVkUQOfEPbsJoytpmNSpCN+m2u6x55lnqBlfVlHlhBkUsE+bGCQubPjDMcBfyYPanRj2vq8A== X-Received: by 2002:a62:a219:: with SMTP id m25mr4396024pff.197.1553188697650; Thu, 21 Mar 2019 10:18:17 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id z6sm20953866pgo.31.2019.03.21.10.18.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 21 Mar 2019 10:18:17 -0700 (PDT) From: Evan Green To: Kishon Vijay Abraham I Cc: Stephen Boyd , Marc Gonzalez , Can Guo , Vivek Gautam , Douglas Anderson , Asutosh Das , Evan Green , Rob Herring , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , Mark Rutland , Rob Herring Subject: [PATCH v5 2/8] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Date: Thu, 21 Mar 2019 10:17:54 -0700 Message-Id: <20190321171800.104681-3-evgreen@chromium.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321171800.104681-1-evgreen@chromium.org> References: <20190321171800.104681-1-evgreen@chromium.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 5d181fc3cc18..4a78ba8b85bc 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -59,7 +59,8 @@ Required properties: one for each entry in reset-names. - reset-names: "phy" for reset of phy block, "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset. + "cfg" for phy's ahb cfg block reset, + "ufsphy" for the PHY reset in the UFS controller. For "qcom,ipq8074-qmp-pcie-phy" must contain: "phy", "common". @@ -74,7 +75,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": no resets are listed. + For "qcom,sdm845-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.