Message ID | 20190123221137.41722-4-evgreen@chromium.org |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | phy: qcom-ufs: Enable regulators to be off in suspend | expand |
Quoting Evan Green (2019-01-23 14:11:31) > Add a resets property to the PHY that represents the PHY reset > register in the UFS controller itself. This better describes the > complete specification of the PHY, and allows the PHY to perform > its initialization in a single function, rather than relying on > back-channel sequencing of initialization through the PHY framework. > > Signed-off-by: Evan Green <evgreen@chromium.org> > Reviewed-by: Rob Herring <robh@kernel.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 21d9a93db2e97..fd59f93e95562 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -29,6 +29,7 @@ Optional properties: - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply +- resets : specifies the PHY reset in the UFS controller Example: @@ -51,9 +52,11 @@ Example: <&clock_gcc clk_ufs_phy_ldo>, <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; + resets = <&ufshc 0>; }; - ufshc@fc598000 { + ufshc: ufshc@fc598000 { + #reset-cells = <1>; ... phys = <&ufsphy1>; phy-names = "ufsphy";