From patchwork Fri Jan 11 23:01:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1023794 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="j/A1RbFd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43byzm3K59z9s9h for ; Sat, 12 Jan 2019 10:01:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726206AbfAKXBz (ORCPT ); Fri, 11 Jan 2019 18:01:55 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:37356 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726198AbfAKXBz (ORCPT ); Fri, 11 Jan 2019 18:01:55 -0500 Received: by mail-pf1-f195.google.com with SMTP id y126so7626739pfb.4 for ; Fri, 11 Jan 2019 15:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vtfQdK+NuZm6RALU79/MbDamjG1NtGBB0yoEpvJy90o=; b=j/A1RbFdkcj+d9WxOzq5gflz9qCLRoEqS5nyzdniPNv8XWUyGr72vOS0hSv23Ccbtd feHfh/83432gvgbGKnkzyKDhnt6n5J1NsQU9OSzoLgYFA6iNI8N2JlhyzaIxWtOWUegJ 9BS997UgvUBMSY74WJjZBb8bkcsKu6T1z5M3E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vtfQdK+NuZm6RALU79/MbDamjG1NtGBB0yoEpvJy90o=; b=gbURIAsZJwhDBCV5QcpbDWuzpdVUkP5/HB8kT9KrNSM9ghfS5rufwGzcCFS3EGnfY5 jLEuAmTt2v/yi3qSd0Q/C2l2EXyw489iRtjq8AdEepWHEXLGZfzXyung8VDzd15FVg1M EFcwlmvqjOzIVJaZvM+DeMM0rnQhd5fwn62mlFHe1tjsAya+0H9zNB/qAu4th2Oy50CT 6o5is77p6+JubQXhEhd8VAnGUTVr8UBluy0QpNqC6HXTW9A3unlV1/muZvEpf5Uu256+ jfBg9bmBiB8Uj7eClkHogIO7H+hAP8jPpsvbEJ3K2DSbrRp26uqVhrAdzzVbb5PF6MDN a6QA== X-Gm-Message-State: AJcUukfWMeReEK6Q9+QkYeVVCqqVmebMmvcbsXKlAKpV7nahin4/KtUT VOi2U6MorxrtdEIpd0pJSuZbjw== X-Google-Smtp-Source: ALg8bN4uExvKt7jxieGS+1JajeiF2AdV1iUktjWmDqNmldP9yYgfT3JaLZLjMUWQgJxtsIRWlKfu7A== X-Received: by 2002:a63:5b1f:: with SMTP id p31mr14893143pgb.56.1547247714944; Fri, 11 Jan 2019 15:01:54 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id 15sm116045186pfr.55.2019.01.11.15.01.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Jan 2019 15:01:54 -0800 (PST) From: Evan Green To: Andy Gross , Rob Herring , Kishon Vijay Abraham I Cc: Can Guo , Douglas Anderson , Asutosh Das , Stephen Boyd , Vivek Gautam , Evan Green , devicetree@vger.kernel.org, Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/8] dt-bindings: phy-qcom-qmp: Add UFS PHY reset Date: Fri, 11 Jan 2019 15:01:22 -0800 Message-Id: <20190111230129.127037-2-evgreen@chromium.org> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20190111230129.127037-1-evgreen@chromium.org> References: <20190111230129.127037-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a required reset to the SDM845 UFS phy to express the PHY reset bit inside the UFS controller register space. Before this change, this reset was not expressed in the DT, and the driver utilized two different callbacks (phy_init and phy_poweron) to implement a two-phase initialization procedure that involved deasserting this reset between init and poweron. This abused the two callbacks and diluted their purpose. That scheme does not work as regulators cannot be turned off in phy_poweroff because they were turned on in init, rather than poweron. The net result is that regulators are left on in suspend that shouldn't be. This new scheme gives the UFS reset to the PHY, so that it can fully initialize itself in a single callback. We can then turn regulators on during poweron and off during poweroff. Signed-off-by: Evan Green Reviewed-by: Rob Herring --- I realize I'm not supposed to add a required property after the fact, but given that the UFS DT nodes that would use this binding are not yet upstream (and this would be the first), I was hoping to squeak by. Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 41a1074228ba7..6b6ca4456dc7c 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -53,7 +53,8 @@ Required properties: one for each entry in reset-names. - reset-names: "phy" for reset of phy block, "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset. + "cfg" for phy's ahb cfg block reset, + "ufsphy" for the PHY reset in the UFS controller. For "qcom,ipq8074-qmp-pcie-phy" must contain: "phy", "common". @@ -65,7 +66,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-usb3-uni-phy" must contain: "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": no resets are listed. + For "qcom,sdm845-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.