From patchwork Sat Dec 15 05:21:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 1013835 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="feuHfR82"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43GwmL6BQbz9s6w for ; Sat, 15 Dec 2018 16:22:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729908AbeLOFWc (ORCPT ); Sat, 15 Dec 2018 00:22:32 -0500 Received: from mail-pf1-f193.google.com ([209.85.210.193]:33557 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729943AbeLOFWb (ORCPT ); Sat, 15 Dec 2018 00:22:31 -0500 Received: by mail-pf1-f193.google.com with SMTP id c123so3814862pfb.0 for ; Fri, 14 Dec 2018 21:22:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OLe9TDsF9ykXoskMy1MUV6N74DR2JxYIMBM3AVcxyko=; b=feuHfR826w2zbdrMCBmO9bQOCB5pu21rH6+y8utGYNdneyOMzlRKZMZ0yZ6M+vo6QB KB7YU4Mml7amEdcxZtogoLH3cVSGI1p8ggWLyDorL91rCi2VxEJkBRh3LBeriDPAtzts 7rAdGGHOIvm52Vd5qsDvAAtByJvDhOzaPj2QTYBjeUwp3MuId1jeeWBRCDsSjFJNP1yA wbTZxQisvd/f92hIBUzBw9Y7Sdq3AE1NHi22vFwvqmgxy9aG82OVeoM2ITXwSARWTdb/ nJztNtNnUVbCHtMvc/+nIamH3xYlWrP4C8GKObR8GSS19l0Tu0mR2p6vcbqExDJlzAru gK/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OLe9TDsF9ykXoskMy1MUV6N74DR2JxYIMBM3AVcxyko=; b=mJET2b4z/zdYRFzQsFOekeXRuXezpZPo/BPt2XCNOy3XWDAxiBMnbDD7Cet4qKA/Z4 RyaimRl0j6+fVFTd6+gXYeYblbNdDrHWY+kCGeBg5zhJXuDAr0mJ3AZM6gPcMCey/pyC wImi4fUuu4vfINqsZ2X3eciVOl0KztpTWTsl2RnmS+1vDCIKP+qKF8HBI3EUS006EeVA k6jFEvBT55g3rQBuuQqZ2fa0k9Nw17zF92Dlo4Ar2GLX3vWlP4XwurtupeixHb7fXtWy /wWg14GxmCw6ibVwTsSWVqbt0z0sDuv77mz3Ji4CoEhwWy+V+JFVOLJyMW8BSZ7+FPpF c4pw== X-Gm-Message-State: AA+aEWbnaEsQM10GK4wPMJplH7AeElDgDCnmCyRAclq+5uI77SNiZPKK VWRjVk+rD4lJblCHChJYrqPFIQ== X-Google-Smtp-Source: AFSGD/VKuAo7dsf/qapsT4rICerC5zin1uQkYOu2fmF1M+PTkeQRU4rRjdtOkiorie6yBwO0+PN5jw== X-Received: by 2002:a63:1b1f:: with SMTP id b31mr5107167pgb.66.1544851350858; Fri, 14 Dec 2018 21:22:30 -0800 (PST) Received: from viisi.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id z127sm11351282pfb.80.2018.12.14.21.22.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Dec 2018 21:22:30 -0800 (PST) From: Paul Walmsley To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Paul Walmsley , Rob Herring , Mark Rutland , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org, Paul Walmsley Subject: [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Date: Fri, 14 Dec 2018 21:21:50 -0800 Message-Id: <20181215052154.24347-4-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20181215052154.24347-1-paul.walmsley@sifive.com> References: <20181215052154.24347-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible strings for the SiFive E51 family of CPU cores to the RISC-V CPU compatible string documentation. The E51 CPU core is described in: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Cc: Rob Herring Cc: Mark Rutland Cc: Palmer Dabbelt Cc: Albert Ou Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley --- Documentation/devicetree/bindings/riscv/cpus.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..fb9d4f86f41f 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -68,8 +68,9 @@ described below. - compatible: Usage: required Value type: - Definition: must contain "riscv", may contain one of - "sifive,rocket0" + Definition: must contain "riscv", may contain one or + more of "sifive,rocket0", "sifive,e51", + "sifive,e5" - mmu-type: Usage: optional Value type: