From patchwork Thu Nov 29 22:13:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 1005689 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="dey1Ix9F"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 435Wz01DWKz9s8r for ; Fri, 30 Nov 2018 09:14:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726389AbeK3JVd (ORCPT ); Fri, 30 Nov 2018 04:21:33 -0500 Received: from mail-pf1-f195.google.com ([209.85.210.195]:41871 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726344AbeK3JVd (ORCPT ); Fri, 30 Nov 2018 04:21:33 -0500 Received: by mail-pf1-f195.google.com with SMTP id b7so1712076pfi.8 for ; Thu, 29 Nov 2018 14:14:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bP09pPsXf42T9CIhAyRDjGi1txaGVY1M+gjxYfwLzTc=; b=dey1Ix9FlQnYJjuEP87TulNMr3tOL3jFcGmfci6IBhriMKkuvfoR/6i+yMlN1e3UUJ OzFdtSdrW5rTjsOCQ3a75qpRrxvHwEnwpaBNVyVOAt1qw0NXkux/vjTcyia8CKH62BFN o3AofoLhiFQx0CezcOboG3fEo/dRTsMqcyPbA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bP09pPsXf42T9CIhAyRDjGi1txaGVY1M+gjxYfwLzTc=; b=CsN5Pmd+Yi7UfXfIyZNYjOey43jMAY/LzTqYs2i3LRN0DXKHr2kTFDXG/P8Axd2XtB 4ksf4+Su7J5gAp+NV2Q2k3Zn1tPpuLPWtVW6ZPPWwmC1bnnY10WBsN/4haE23bgPAVhH We6+P+RW9zZiANumpXznmDfJCiw1YHOuFJZtY09zTlbDo3Sgxy5nkrmMtbpZVmrybbFv 5Ja8KZ2LXnJ4MHBpbeWOWRTC7duezexyqvux83nLOw8yHfGeYTUbaJfWV3RnDHHGQTeD PRtG5FbVgEgR4fVfBjONRyNo3l8YmtOc0RrTE9y2pvbbvn8bpj1Tbai/SqwJYO+r4/vt dGFg== X-Gm-Message-State: AA+aEWYVcUTe5/WQKzuM70z10DUfy4QHWpo++jly9B7+ALEwc5Bfrkzi wbuPw5jsDqSEpxpVEk8q6iVFxg== X-Google-Smtp-Source: AFSGD/XQsbXA9jf85glzSn5/uAW7iEAOHbjpPW7TD+RWRQMZqcLaJvsMfB5+4VhlnwFQnXB6CtV55w== X-Received: by 2002:a62:5182:: with SMTP id f124mr3171044pfb.238.1543529674780; Thu, 29 Nov 2018 14:14:34 -0800 (PST) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:ffda:7716:9afc:1301]) by smtp.gmail.com with ESMTPSA id c67sm4697690pfg.170.2018.11.29.14.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Nov 2018 14:14:34 -0800 (PST) From: Evan Green To: Kishon Vijay Abraham I , Rob Herring , Andy Gross Cc: Douglas Anderson , Stephen Boyd , Evan Green , devicetree@vger.kernel.org, Mark Rutland , linux-kernel@vger.kernel.org Subject: [PATCH v1 1/4] dt-bindings: phy-qcom-qmp: Move #clock-cells to child Date: Thu, 29 Nov 2018 14:13:54 -0800 Message-Id: <20181129221357.67417-2-evgreen@chromium.org> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181129221357.67417-1-evgreen@chromium.org> References: <20181129221357.67417-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The phy-qcom-qmp bindings specified #clock-cells as 1. This was never used because of_clk_add_provider() was never called, so there was no way anybody could reference these clocks from DT. Furthermore, even if they could be accessed, the bindings never specified what should go in that additional cell. Fix these incomplete and broken bindings. Move the #clock-cells into the child node, since that is the actual clock provider, and not all instances of qcom-qmp-phy are clock providers. Also set #clock-cells to zero, since there's nothing to pass to it. Signed-off-by: Evan Green Reviewed-by: Stephen Boyd --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index f7b532125a4d9..41a1074228ba7 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -25,10 +25,6 @@ Required properties: - For all others: - The reg-names property shouldn't be defined. - - #clock-cells: must be 1 (PCIe and USB3 PHYs only) - - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe - interface (for pipe based PHYs). These clock are then gate-controlled - by gcc. - #address-cells: must be 1 - #size-cells: must be 1 - ranges: must be present @@ -106,6 +102,9 @@ Required properties for child node of PCIe and USB3 qmp phys: - "pcie20_phy0_pipe_clk" Pipe Clock parent (or) "pcie20_phy1_pipe_clk" + - #clock-cells: must be 0 + - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then + gate-controlled by the gcc. Required properties for child node of PHYs with lane reset, AKA: "qcom,msm8996-qmp-pcie-phy" @@ -118,7 +117,6 @@ Example: phy@34000 { compatible = "qcom,msm8996-qmp-pcie-phy"; reg = <0x34000 0x488>; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -140,6 +138,7 @@ Example: reg = <0x35000 0x130>, <0x35200 0x200>, <0x35400 0x1dc>; + #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; @@ -157,7 +156,6 @@ Example: phy@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; reg = <0x88eb000 0x18c>; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -177,6 +175,7 @@ Example: <0x88eb400 0x1fc>, <0x88eb800 0x218>, <0x88eb600 0x70>; + #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "pipe0";