From patchwork Mon Nov 12 15:23:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 996502 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="b6y9GgLs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvgN5Nnkz9s3C for ; Tue, 13 Nov 2018 02:24:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729488AbeKMBRf (ORCPT ); Mon, 12 Nov 2018 20:17:35 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:41830 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729452AbeKMBRe (ORCPT ); Mon, 12 Nov 2018 20:17:34 -0500 Received: by mail-wr1-f65.google.com with SMTP id v18-v6so9801885wrt.8 for ; Mon, 12 Nov 2018 07:23:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+scvbKSgWS1sZ8YB01SJV/sDev8JcNZzuzRnAPkaFfU=; b=b6y9GgLsXE2zRQnjmQunelvLgg8c9S0wwRJK0W/oiYfTleWd3qPPEJApTjNUCCq1EE uaozXLjzqYz84qZx6+GQRfk9u5zF9wjXRzAnEfyd7g5iykFth4NhXtDktP1yC+M3mIau 3mKYNxogJxOm+cDKkyc/0ftEVUj9LKTcW90lo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+scvbKSgWS1sZ8YB01SJV/sDev8JcNZzuzRnAPkaFfU=; b=k53dpuG+r7T8pZSfcWPrwjbrveYJ+Y/skNA9tKBHWC1zHf068pi7wK7mhfKX3+nZhv oK2cXdlbBrskowRUDp6uN01sDovighRM5sGs0sVWh87/1XX3T2+6KbwoXNw/cfHBUnoP /cLccueImimz6vAJAOOA2pTXPZ3ypU75zYhFf3+OKYw2COS0ZRB7CGi9q+ye/bdDU/1v GYnOrrD8EIpqQSDWD2HTDZ3rx+HuIpYbCO76r9BcrQi+xtsD0vX7AsYrFsSV0IcLFTSw aNbmI6un+TncYChzli+L+3Gj5AP6IkqEHOPv+u2/AZKL0KABiNs624YZ3n6ctAqPzQAk HxqA== X-Gm-Message-State: AGRZ1gKKzq0SlmUuboLE0WVZOaq7DxhVF2oNJznyQqC3ZFhCQrO9Hvzm PZR8UmQU0WmE9j1sr7qKxj1p4g== X-Google-Smtp-Source: AJdET5eOqBQjVl2aY+ctwq8SwBfWpS6FCukxRI6DOeEBlq0uijcaAowAORTWJaIuYZfbUC+ORgVSvg== X-Received: by 2002:a5d:410d:: with SMTP id l13-v6mr1363524wrp.61.1542036230916; Mon, 12 Nov 2018 07:23:50 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105e:a8d5:7c2c:2737:d373:11ee]) by smtp.gmail.com with ESMTPSA id t82-v6sm11192849wme.30.2018.11.12.07.23.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 07:23:50 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v3 1/4] dt-bindings: hwlock: Document STM32 hwspinlock bindings Date: Mon, 12 Nov 2018 16:23:39 +0100 Message-Id: <20181112152342.6561-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20181112152342.6561-1-benjamin.gaignard@st.com> References: <20181112152342.6561-1-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings for STM32 hardware spinlock device Signed-off-by: Benjamin Gaignard Reviewed-by: Rob Herring --- version 3 : - fix clock name in properties description version 2 : - change clock name from hwspinlock to hsem to be align with hardware documentation .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt new file mode 100644 index 000000000000..adf4f000ea3d --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -0,0 +1,23 @@ +STM32 Hardware Spinlock Device Binding +------------------------------------- + +Required properties : +- compatible : should be "st,stm32-hwspinlock". +- reg : the register address of hwspinlock. +- #hwlock-cells : hwlock users only use the hwlock id to represent a specific + hwlock, so the number of cells should be <1> here. +- clock-names : Must contain "hsem". +- clocks : Must contain a phandle entry for the clock in clock-names, see the + common clock bindings. + +Please look at the generic hwlock binding for usage information for consumers, +"Documentation/devicetree/bindings/hwlock/hwlock.txt" + +Example of hwlock provider: + hwspinlock@4c000000 { + compatible = "st,stm32-hwspinlock"; + #hwlock-cells = <1>; + reg = <0x4c000000 0x400>; + clocks = <&rcc HSEM>; + clock-names = "hsem"; + };