From patchwork Thu Oct 18 21:09:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 986300 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="PRGf1TMO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42bhWf6kCvz9s8J for ; Fri, 19 Oct 2018 08:09:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727404AbeJSFMl (ORCPT ); Fri, 19 Oct 2018 01:12:41 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:44053 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725738AbeJSFMl (ORCPT ); Fri, 19 Oct 2018 01:12:41 -0400 Received: by mail-pl1-f195.google.com with SMTP id d23-v6so1421007pls.11 for ; Thu, 18 Oct 2018 14:09:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jnOVjzaA3k+wL7/rkNrM4EYBgeAj3EhUbVMeYHm1XMU=; b=PRGf1TMOfyKUiP184cLZqkqH1PiUf8yjyb6hwi5I/QF/McUtzOFHLJB70N6vHYFz93 cUb2fDSWUntm/uTDL18iK+wXFHjSRc9blSqmfOppjXTbbWmQ3E0DFqeD63fQnWG5TGAw qy8wKIqeWxhzpvZrgj1NanMsjiPRtD2MhqOas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jnOVjzaA3k+wL7/rkNrM4EYBgeAj3EhUbVMeYHm1XMU=; b=WwkBq9abki1txOJktSAymZW/cxyWPXUf2J+zt9wXcBU3QO/JCuoUID0dUJUz4AAdaw xZnvingU3dZcXid5BZqju5S8ncZwgtuIotI9W1JsdLhVffn76fyMQzxWoo8Zc5KT+SQp iMP/P/npDc0rCu1JwxQEoPnb7pjLGrjrZksVKMVaAgP6ZAxHpWKQ23Wjr7+pUFXL4LMV JAMrOowrX9s92zRYR/BaVTPH0+7ZY7lg/7ZNSzxenFA9h8nUTMyjR3oKexGwbrOo+s+W md/T95kTKL2x5zJVJcmyXt0dMbi6hUxGnUVYWOoiYZknUG8Fz2tBWao1PDZn5Dq6l8oV 7f/g== X-Gm-Message-State: ABuFfogaStznsum+DOXyt1PJArW22G4cEGynnjEE3chDq9m3TwxN2FQ8 VlTfMEmvdOiRQQ75zN5k8BU5Kw== X-Google-Smtp-Source: ACcGV60GZK5TQP4o14T/NwTlxpgv2EWI/xzShu1U22BJeJYnHCyKjiVFlT5g9wajfthr5Pd1v1Wkqw== X-Received: by 2002:a17:902:e111:: with SMTP id cc17-v6mr31350314plb.175.1539896989191; Thu, 18 Oct 2018 14:09:49 -0700 (PDT) Received: from evgreen2.mtv.corp.google.com ([2620:15c:202:201:e418:c825:76cf:5f64]) by smtp.gmail.com with ESMTPSA id i29-v6sm35133678pfj.82.2018.10.18.14.09.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Oct 2018 14:09:48 -0700 (PDT) From: Evan Green To: Rob Herring , Mark Rutland , Andy Gross , David Brown , Kishon Vijay Abraham I , Douglas Anderson , Manu Gautam , Can Guo , Vivek Gautam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, swboyd@chromium.org Cc: Evan Green Subject: [PATCH v2 1/5] dt-bindings: phy-qcom-qmp: Fix register underspecification Date: Thu, 18 Oct 2018 14:09:29 -0700 Message-Id: <20181018210933.113592-2-evgreen@chromium.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181018210933.113592-1-evgreen@chromium.org> References: <20181018210933.113592-1-evgreen@chromium.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This change adds register regions for the second lane of dual-lane nodes. This additional specification is needed so that the driver can stop reaching beyond the tx and rx register allocations to get at the second lane registers in a dual-lane PHY. While in there, document #clock-cells as optional for PHYs that don't provide a pipe clock. Also, document the pcs_misc register region, which was being quietly supplied and used. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Reviewed-by: Rob Herring --- This applies atop linux-next 20181018 with the addition of Doug's changes [1] and [2]. [1] https://lore.kernel.org/lkml/20181012213632.252346-1-dianders@chromium.org/ [2] https://lore.kernel.org/lkml/20181012213926.253765-1-dianders@chromium.org/ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 73 +++++++++++++++++++--- 1 file changed, 65 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index fbc198d5dd39..297a7c753fc8 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -25,7 +25,7 @@ Required properties: - For all others: - The reg-names property shouldn't be defined. - - #clock-cells: must be 1 + - #clock-cells: must be 1 (PCIe and USB3 PHYs only) - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe interface (for pipe based PHYs). These clock are then gate-controlled by gcc. @@ -82,23 +82,26 @@ Required nodes: - Each device node of QMP phy is required to have as many child nodes as the number of lanes the PHY has. -Required properties for child node: +Required properties for child nodes of PCIe PHYs (one child per lane): - reg: list of offset and length pairs of register sets for PHY blocks - - - index 0: tx - - index 1: rx - - index 2: pcs - - index 3: pcs_misc (optional) + tx, rx, pcs, and pcs_misc (optional). + - #phy-cells: must be 0 +Required properties for a single "lanes" child node of non-PCIe PHYs: + - reg: list of offset and length pairs of register sets for PHY blocks + For 1-lane devices: + tx, rx, pcs, and (optionally) pcs_misc + For 2-lane devices: + tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc - #phy-cells: must be 0 -Required properties child node of pcie and usb3 qmp phys: +Required properties for child node of PCIe and USB3 qmp phys: - clocks: a list of phandles and clock-specifier pairs, one for each entry in clock-names. - clock-names: Must contain following: "pipe" for pipe clock specific to each lane. - clock-output-names: Name of the PHY clock that will be the parent for the above pipe clock. - For "qcom,ipq8074-qmp-pcie-phy": - "pcie20_phy0_pipe_clk" Pipe Clock parent (or) @@ -150,3 +153,57 @@ Example: ... ... }; + + phy@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0x88eb000 0x18c>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + lane@88eb200 { + reg = <0x88eb200 0x128>, + <0x88eb400 0x1fc>, + <0x88eb800 0x218>, + <0x88e9600 0x70>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + lanes@1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>, + <0x1d87800 0x108>, + <0x1d87a00 0x1e0>; + #phy-cells = <0>; + }; + };