From patchwork Sat Aug 4 07:03:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emmanuel Vadot X-Patchwork-Id: 953413 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=freebsd.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41jFJX6pthz9s0R for ; Sat, 4 Aug 2018 17:04:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726550AbeHDJDs (ORCPT ); Sat, 4 Aug 2018 05:03:48 -0400 Received: from mx2.freebsd.org ([8.8.178.116]:59333 "EHLO mx2.freebsd.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbeHDJDs (ORCPT ); Sat, 4 Aug 2018 05:03:48 -0400 Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mx1.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx2.freebsd.org (Postfix) with ESMTPS id 7B84F664FD; Sat, 4 Aug 2018 07:04:10 +0000 (UTC) (envelope-from manu@freebsd.org) Received: from smtp.freebsd.org (smtp.freebsd.org [96.47.72.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "smtp.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C37C288E31; Sat, 4 Aug 2018 07:04:09 +0000 (UTC) (envelope-from manu@freebsd.org) Received: from skull.home.blih.net (ip-9.net-89-3-105.rev.numericable.fr [89.3.105.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) (Authenticated sender: manu) by smtp.freebsd.org (Postfix) with ESMTPSA id 4566F15D4E; Sat, 4 Aug 2018 07:04:08 +0000 (UTC) (envelope-from manu@freebsd.org) From: Emmanuel Vadot To: rui.zhang@intel.com, edubezval@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@bootlin.com, wens@csie.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Emmanuel Vadot Subject: [PATCH 1/7] dt-bindings: Add DT bindings documentation for Allwinner Thermal Sensor Controller Date: Sat, 4 Aug 2018 09:03:49 +0200 Message-Id: <20180804070355.14857-1-manu@freebsd.org> X-Mailer: git-send-email 2.18.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds documentation for Device-Tree bindings for the Allwinner Thermal Sensor Controller found on the H3, H5 and A64 SoCs Signed-off-by: Emmanuel Vadot --- .../bindings/thermal/allwinner-thermal.txt | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/allwinner-thermal.txt diff --git a/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt b/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt new file mode 100644 index 000000000000..5810d44cf495 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/allwinner-thermal.txt @@ -0,0 +1,41 @@ +* Thermal Sensor Controller on Allwinner SoCs + +Required properties: +- compatible : should be "allwinner,-ths" + "allwinner,sun8i-h3-ths": found on H3 and H2+ SoCs + "allwinner,sun50i-h5-ths": found on H5 SoC + "allwinner,sun50i-a64-ths": found on H5 SoC +- reg : physical base address of the controller and length of memory mapped + region. +- interrupts : The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Shall be "apb" for the bus, and "ths" for + the peripheral clock. +- resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names : Must be "apb". +- #thermal-sensor-cells : Depend on the SoC + For H3 should be 0 + For H5 should be 1 + For A64 should be 2 + See ./thermal.txt for a description. +- nvmem-cells : Phandle to the calibration data +- nvmem-cell-names = Should be "ths-calib" + +Example: + +ths: thermal_sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "apb", "ths"; + resets = <&ccu RST_BUS_THS>; + reset-names = "apb"; + #thermal-sensor-cells = <0>; + status = "disabled"; + + nvmem-cells = <&ths_calib>; + nvmem-cell-names = "ths-calib"; +};