@@ -1,8 +1,10 @@
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
-- compatible : "snps,dw-apb-ssi"
-- reg : The register base for the controller.
+- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
+ "jaguar2"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+ register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
The integration of the Designware SPI controller on Microsemi SoCs requires an extra register set to be able to give the IP control of the SPI interface. Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> --- Changes in v4: - changed subject to be prefixed by spi: dw: - documented possible <soc> values. jaguar2 support will be added later to the driver. Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)