| Message ID | 20180212070847.32387-2-joel@jms.id.au |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | misc: aspeed-lpc-ctrl fixes | expand |
On Mon, 2018-02-12 at 17:38 +1030, Joel Stanley wrote: > The LPC Host Interface Controller is part of a BMC SoC that is used for > communication with the host. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 40 ++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > index 514d82ced95b..94a31de109c4 100644 > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt > @@ -109,6 +109,46 @@ lpc: lpc@1e789000 { > }; > }; > > +BMC Node Children > +================== > + > +LPC Host Interface Controller This should be under the Host Node Children header given the function's position in the MMIO layout and the split prescribed by the bindings. > +------------------- > + > +The LPC Host Interface Controller manages functions exposed to the host such as > +LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART > +management and bus snoop configuration. > + > +Required properties: > + > +- compatible: One of: > + "aspeed,ast2400-lpc-ctrl"; > + "aspeed,ast2500-lpc-ctrl"; > + > +- reg: contains offset/length values of the host interface controller > + memory regions > + > +- clocks: contains a phandle to the syscon node describing the clocks. > + There should then be one cell representing the clock to use > + > +- memory-region: A phandle to a reserved_memory region to be used for the LPC > + to AHB mapping > + > +- flash: A phandle to the SPI flash controller containing the flash to > + be exposed over the LPC to AHB mapping > + > +Example: > + > +lpc-host@80 { > + lpc_ctrl: lpc-ctrl@0 { > + compatible = "aspeed,ast2500-lpc-ctrl"; > + reg = <0x0 0x80>; > + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; > + memory-region = <&flash_memory>; > + flash = <&spi>; > + }; > +}; ACK wrt the content, just need to fix its location. > + > Host Node Children > ================== >
On Mon, Feb 12, 2018 at 05:38:45PM +1030, Joel Stanley wrote: > The LPC Host Interface Controller is part of a BMC SoC that is used for > communication with the host. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > .../devicetree/bindings/mfd/aspeed-lpc.txt | 40 ++++++++++++++++++++++ > 1 file changed, 40 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index 514d82ced95b..94a31de109c4 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -109,6 +109,46 @@ lpc: lpc@1e789000 { }; }; +BMC Node Children +================== + +LPC Host Interface Controller +------------------- + +The LPC Host Interface Controller manages functions exposed to the host such as +LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART +management and bus snoop configuration. + +Required properties: + +- compatible: One of: + "aspeed,ast2400-lpc-ctrl"; + "aspeed,ast2500-lpc-ctrl"; + +- reg: contains offset/length values of the host interface controller + memory regions + +- clocks: contains a phandle to the syscon node describing the clocks. + There should then be one cell representing the clock to use + +- memory-region: A phandle to a reserved_memory region to be used for the LPC + to AHB mapping + +- flash: A phandle to the SPI flash controller containing the flash to + be exposed over the LPC to AHB mapping + +Example: + +lpc-host@80 { + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; +}; + Host Node Children ==================
The LPC Host Interface Controller is part of a BMC SoC that is used for communication with the host. Signed-off-by: Joel Stanley <joel@jms.id.au> --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+)