From patchwork Mon Jan 22 09:21:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 864196 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=prevas.dk header.i=@prevas.dk header.b="HIXq/w69"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zQ5ZW2BVYz9s71 for ; Mon, 22 Jan 2018 20:23:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751097AbeAVJWP (ORCPT ); Mon, 22 Jan 2018 04:22:15 -0500 Received: from mail02.prevas.se ([62.95.78.10]:3319 "EHLO mail02.prevas.se" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751433AbeAVJVy (ORCPT ); Mon, 22 Jan 2018 04:21:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=prevas.dk; i=@prevas.dk; l=2253; q=dns/txt; s=ironport2; t=1516612913; x=1548148913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=9szoMeSFX6gMSopcdxnuP+9wXRjfEGx3z8DEo3/HScQ=; b=HIXq/w69e6Th6I+HUVuf0VdubFD1WvqR01U5pF0+b4qWc1VpBjt01B6U m53Han1xpTnjPl63Rg/4taJdaZOKNG+XPj8W3Gyw0huyxjZa7OahZHI06 Ly9tJLIzG0h0t7iLHav+wUPYCWSb9klEpAULJt1Dx3Am3Pvhtcaeqt0QL k=; X-IronPort-AV: E=Sophos;i="5.46,396,1511823600"; d="scan'208";a="2945087" Received: from vmprevas4.prevas.se (HELO smtp.prevas.se) ([172.16.8.104]) by ironport2.prevas.se with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jan 2018 10:21:52 +0100 Received: from prevas-ravi.prevas.se (172.16.8.31) by smtp.prevas.se (172.16.8.104) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 22 Jan 2018 10:21:52 +0100 From: Rasmus Villemoes To: Rob Herring , Shawn Guo , Thomas Gleixner , Jason Cooper , Marc Zyngier , Mark Rutland CC: Andy Tang , Alexander Stein , Rasmus Villemoes , , Subject: [PATCH v3 2/2] dt/bindings: Add bindings for Layerscape external irqs Date: Mon, 22 Jan 2018 10:21:33 +0100 Message-ID: <20180122092133.23177-2-rasmus.villemoes@prevas.dk> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180122092133.23177-1-rasmus.villemoes@prevas.dk> References: <1513758631-19909-1-git-send-email-rasmus.villemoes@prevas.dk> <20180122092133.23177-1-rasmus.villemoes@prevas.dk> MIME-Version: 1.0 X-Originating-IP: [172.16.8.31] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Rasmus Villemoes --- .../interrupt-controller/fsl,ls-extirq.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt new file mode 100644 index 000000000000..a71ce2c3eeae --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -0,0 +1,44 @@ +* Freescale Layerscape external IRQs + +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +the polarity of certain external interrupt lines. + +The device node must be a child of the node representing the +Supplemental Configuration Unit (SCFG). + +Required properties: +- compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: Use the same format as specified by GIC in arm,gic.txt. +- interrupt-parent: phandle of GIC. +- offset: offset to the Interrupt Polarity Control Register (INTPCR) + register in the SCFG. +- interrupts: Specifies the mapping to interrupt numbers in the parent + interrupt controller. Interrupts are mapped one-to-one to parent + interrupts. + +Optional properties: +- fsl,bit-reverse: This boolean property should be set on the LS1021A + if the SCFGREVCR register has been set to all-ones (which is usually + the case), meaning that all reads and writes of SCFG registers are + implicitly bit-reversed. Other compatible platforms do not have such + a register. + +Example: + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + ... + extirq: interrupt-controller { + compatible = "fsl,ls1021a-extirq"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + offset = <0x1ac>; + interrupts = <163 164 165 167 168 169>; + fsl,bit-reverse; + }; + }; + + + interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <&extirq GIC_SPI 1 IRQ_TYPE_LEVEL_LOW>;