From patchwork Mon Oct 30 07:22:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 831903 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="G5URWAe3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQQt91yQbz9t3B for ; Mon, 30 Oct 2017 18:22:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751460AbdJ3HWj (ORCPT ); Mon, 30 Oct 2017 03:22:39 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:48961 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751451AbdJ3HWi (ORCPT ); Mon, 30 Oct 2017 03:22:38 -0400 Received: by mail-pf0-f196.google.com with SMTP id b79so10306472pfk.5; Mon, 30 Oct 2017 00:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=Dpts089VMeXGSKHtnaLwV2bao8NhZwJfqKldsRHy4GQ=; b=G5URWAe3EwfVRCP5ICr6vM0Agx5czxRla6UJve1a0PN+AOa6/np5XFCUAkdZHUnS0N aUPlOA/ROIBRJufX56cgoIMQxZGV8dlac1sW9K7TSnVuG6CXDQ8zijMmYMNYjDtlNbCo +VJMIYoDBbpnExGreI5z3LAO349pRLt5EjUOnz3ZkxjhDQMQqS0kUkKXWiKh5fMp6jaX x1EPFExq2sVkqe5ftP1anz2/nfvvP6aMjXTWhtBTYcBDSZs3IrUSi63G8WZy375lw/aO TS5tFwUQoarqYXqjinyqI88kpQHp9sl1aBjztSZiSVgnFkDypaqphpm6W5FZD2MEM0P5 n3SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=Dpts089VMeXGSKHtnaLwV2bao8NhZwJfqKldsRHy4GQ=; b=fb6ILVJ57ZuamQBIUvdHlbE9N2ZrtCcVld1HptCsbjxJOLOsBGZPqpwKYyh88mlGWU cqxbIgCEJ47PJIamtqL5pbFM3GPp57QG5VSSPJS5A31h6CSUBw8S5WjA77AYup8PW6ZE f02n1O7EGcjwhSfSrlspFSEhgJ9x6R22zqZdQFT3eR4MhyfHL4tf25gLz9GbwiiWEsaB smUPP9AK7aEgFfruLSuT00Nw8YeMZw3C+NBUN/1ETsaDrZBIfkxOHqGeR42VchHfbpdJ niC3n6PsaXseXFRa4uZzRYSC+YblimaeQbFpZ6DvMEbSAEem1DPNcAunj5WAYq0RR8fe hn7g== X-Gm-Message-State: AMCzsaX9Qs+VtqXxksTzbUoeRG9bRhZIJh1HwvCTHq02bFIp9HXoQKvA R6aErZhp1pO3mNOkap7zzH0= X-Google-Smtp-Source: ABhQp+Q6PGJEB/OS+jcRUGRDnKJrxRpxrguSfRW3J97Iz7EOhz+EiJBOoqbGxGrmDqkLOAuOH1epZA== X-Received: by 10.101.67.137 with SMTP id m9mr6811252pgp.51.1509348157396; Mon, 30 Oct 2017 00:22:37 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id l79sm28846726pfb.33.2017.10.30.00.22.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Oct 2017 00:22:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 30 Oct 2017 17:52:28 +1030 From: Joel Stanley To: Jonathan Cameron , Rick Altherr , Rob Herring Cc: Philipp Zabel , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] iio: adc: aspeed: Deassert reset in probe Date: Mon, 30 Oct 2017 17:52:18 +1030 Message-Id: <20171030072218.2094-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ASPEED SoC must deassert a reset in order to use the ADC peripheral. The device tree bindings are updated to document the resets phandle, and the example is updated to match what is expected for both the reset and clock phandle. Signed-off-by: Joel Stanley --- .../devicetree/bindings/iio/adc/aspeed_adc.txt | 4 +++- drivers/iio/adc/aspeed_adc.c | 21 ++++++++++++++++----- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt index 674e133b7cd7..034fc2ba100e 100644 --- a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt @@ -8,6 +8,7 @@ Required properties: - reg: memory window mapping address and length - clocks: Input clock used to derive the sample clock. Expected to be the SoC's APB clock. +- resets: Reset controller phandle - #io-channel-cells: Must be set to <1> to indicate channels are selected by index. @@ -15,6 +16,7 @@ Example: adc@1e6e9000 { compatible = "aspeed,ast2400-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; }; diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 8a958d5f1905..0fc9712cdde4 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -53,11 +54,12 @@ struct aspeed_adc_model_data { }; struct aspeed_adc_data { - struct device *dev; - void __iomem *base; - spinlock_t clk_lock; - struct clk_hw *clk_prescaler; - struct clk_hw *clk_scaler; + struct device *dev; + void __iomem *base; + spinlock_t clk_lock; + struct clk_hw *clk_prescaler; + struct clk_hw *clk_scaler; + struct reset_control *rst; }; #define ASPEED_CHAN(_idx, _data_reg_addr) { \ @@ -217,6 +219,13 @@ static int aspeed_adc_probe(struct platform_device *pdev) goto scaler_error; } + data->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + if (IS_ERR(data->rst)) { + dev_err(&pdev->dev, "invalid reset controller in device tree"); + data->rst = NULL; + } else + reset_control_deassert(data->rst); + model_data = of_device_get_match_data(&pdev->dev); if (model_data->wait_init_sequence) { @@ -268,6 +277,7 @@ static int aspeed_adc_probe(struct platform_device *pdev) scaler_error: clk_hw_unregister_divider(data->clk_prescaler); + reset_control_assert(data->rst); return ret; } @@ -282,6 +292,7 @@ static int aspeed_adc_remove(struct platform_device *pdev) clk_disable_unprepare(data->clk_scaler->clk); clk_hw_unregister_divider(data->clk_scaler); clk_hw_unregister_divider(data->clk_prescaler); + reset_control_assert(data->rst); return 0; }