From patchwork Tue Oct 24 17:57:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 829991 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="j756uIbJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yM1N65mp1z9s1h for ; Wed, 25 Oct 2017 05:03:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751857AbdJXSAw (ORCPT ); Tue, 24 Oct 2017 14:00:52 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:55585 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751550AbdJXSAr (ORCPT ); Tue, 24 Oct 2017 14:00:47 -0400 Received: by mail-wm0-f65.google.com with SMTP id u138so18003014wmu.4; Tue, 24 Oct 2017 11:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UMM2kpygjM3ek2bWrvIGFZpMgdSoTji0+K4C3Cfcdqk=; b=j756uIbJfoV2gkyLhwKxTWpvtfxEFYOTvfAqCxvm12EVFQ8MHm88uW38ts3nhu6U6P eEJLeFnyqdZAsNWnEm4+gGAnIEZyq6CWY+UmN/uDrsdZY5Tjlg50KO0SxBQMDR4g0AAz HoejObpCIsP3qZ8fSYBuSuRoInzIuTSYosTjuwdGZ7CNtF8Sx3nhrjO1KhT7k+V8rumj LcztFjlwG9uN2LXMzlTcIzR6nwU8VS5Y8re6W0T0sQ7iWGTpj7qwUhOCsvfsIMWgWuoQ bvMdw7pIq5MkdFQ4DSp8dVcK1BijyyxBdBY1i1DvMtGO/PT9SjSouT/7gvSVUEA7zFp7 hquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UMM2kpygjM3ek2bWrvIGFZpMgdSoTji0+K4C3Cfcdqk=; b=Tzfje6nJzXa37IXHSNt1U1Bpo9tQa9tajb+v5DOqf7RqLi0eSEtdF+p3ML4FMiKhEP vc7I2GIEhxI03l1C/ro6x2AiX+nXsxzxW8zG3pYKdyWYSTN9JdKsD4VOGfnRhP/gRl2d 5DIrYpKCYHHDCR2jcycWJ5I3LbgoKpzK8qcSAYsgGHasSYYP8Z2jWC/E6L/H7k54Fwtl MqlRY13M3szfF1kXghfg7ASz2mKuL5WGhHuzdGTc9CLOtYwoSRWsgVvZf4W28+D+U/jQ kSH7EN+zEqBBxJlODcLVvyKS+u8QOFyHTxZk0GihuQW260zrRnlYGa0Whkh4Sih/Q4p3 4Dew== X-Gm-Message-State: AMCzsaUaiMpsleO3M9Re9R56QizN45KUC41Q+i1N0MeyQoMYxZRp/sHi vCX6g8YHEzT9v3d7NUhlJ/E= X-Google-Smtp-Source: ABhQp+Q6aibXI1UBxgnde90BqEMXCZiqLDWxwBRSw9lTFrzIfVHyUKGPdV2BLZ+eJMVqgo7CEsObvA== X-Received: by 10.28.66.25 with SMTP id p25mr1987499wma.154.1508868045672; Tue, 24 Oct 2017 11:00:45 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s18sm818968wrg.87.2017.10.24.11.00.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Oct 2017 11:00:45 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v9 02/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Tue, 24 Oct 2017 19:57:06 +0200 Message-Id: <20171024175714.15840-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171024175714.15840-1-clabbe.montjoie@gmail.com> References: <20171024175714.15840-1-clabbe.montjoie@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe Reviewed-by: Andrew Lunn Acked-by: Rob Herring --- .../devicetree/bindings/net/dwmac-sun8i.txt | 145 +++++++++++++++++++-- 1 file changed, 133 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..2600ce9ad3cc 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,42 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the emac node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "allwinner,sun8i-h3-mdio-mux" + - mdio-parent-bus: a phandle to EMAC mdio + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Additional information regarding generic multiplexer properties can be found +at Documentation/devicetree/bindings/net/mdio-mux.txt + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +91,115 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + mdio-parent-bus = <&mdio0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + mdio-parent-bus = <&mdio0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; };